details

property	value
status	complete
benchmark	Ex1_Zan97_C.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n166.star.cs.uiowa.edu
space	Transformed_CSR_innermost_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	72.2995 seconds
cpu usage	72.2044
user time	65.7003
system time	6.50409
max virtual memory	738096.0
max residence set size	33940.0

stage attributes

key	value
starexec-result	YES

output

72.14/72.29 YES 72.14/72.29 72.14/72.29 Problem 1: 72.14/72.29 72.14/72.29 (VAR v_NonEmpty:S X:S) 72.14/72.29 (RULES 72.14/72.29 active(g(X:S)) -> mark(h(X:S)) 72.14/72.29 active(h(d)) -> mark(g(c)) 72.14/72.29 active(c) -> mark(d) 72.14/72.29 g(ok(X:S)) -> ok(g(X:S)) 72.14/72.29 h(ok(X:S)) -> ok(h(X:S)) 72.14/72.29 proper(g(X:S)) -> g(proper(X:S)) 72.14/72.29 proper(h(X:S)) -> h(proper(X:S)) 72.14/72.29 proper(c) -> ok(c) 72.14/72.29 proper(d) -> ok(d) 72.14/72.29 top(mark(X:S)) -> top(proper(X:S)) 72.14/72.29 top(ok(X:S)) -> top(active(X:S)) 72.14/72.29 ) 72.14/72.29 (STRATEGY INNERMOST) 72.14/72.29 72.14/72.29 Problem 1: 72.14/72.29 72.14/72.29 Dependency Pairs Processor: 72.14/72.29 -> Pairs: 72.14/72.29 ACTIVE(g(X:S)) -> H(X:S) 72.14/72.29 G(ok(X:S)) -> G(X:S) 72.14/72.29 H(ok(X:S)) -> H(X:S) 72.14/72.29 PROPER(g(X:S)) -> G(proper(X:S)) 72.14/72.29 PROPER(g(X:S)) -> PROPER(X:S) 72.14/72.29 PROPER(h(X:S)) -> H(proper(X:S)) 72.14/72.29 PROPER(h(X:S)) -> PROPER(X:S) 72.14/72.29 TOP(mark(X:S)) -> PROPER(X:S) 72.14/72.29 TOP(mark(X:S)) -> TOP(proper(X:S)) 72.14/72.29 TOP(ok(X:S)) -> ACTIVE(X:S) 72.14/72.29 TOP(ok(X:S)) -> TOP(active(X:S)) 72.14/72.29 -> Rules: 72.14/72.29 active(g(X:S)) -> mark(h(X:S)) 72.14/72.29 active(h(d)) -> mark(g(c)) 72.14/72.29 active(c) -> mark(d) 72.14/72.29 g(ok(X:S)) -> ok(g(X:S)) 72.14/72.29 h(ok(X:S)) -> ok(h(X:S)) 72.14/72.29 proper(g(X:S)) -> g(proper(X:S)) 72.14/72.29 proper(h(X:S)) -> h(proper(X:S)) 72.14/72.29 proper(c) -> ok(c) 72.14/72.29 proper(d) -> ok(d) 72.14/72.29 top(mark(X:S)) -> top(proper(X:S)) 72.14/72.29 top(ok(X:S)) -> top(active(X:S)) 72.14/72.29 72.14/72.29 Problem 1: 72.14/72.29 72.14/72.29 SCC Processor: 72.14/72.29 -> Pairs: 72.14/72.29 ACTIVE(g(X:S)) -> H(X:S) 72.14/72.29 G(ok(X:S)) -> G(X:S) 72.14/72.29 H(ok(X:S)) -> H(X:S) 72.14/72.29 PROPER(g(X:S)) -> G(proper(X:S)) 72.14/72.29 PROPER(g(X:S)) -> PROPER(X:S) 72.14/72.29 PROPER(h(X:S)) -> H(proper(X:S)) 72.14/72.29 PROPER(h(X:S)) -> PROPER(X:S) 72.14/72.29 TOP(mark(X:S)) -> PROPER(X:S) 72.14/72.29 TOP(mark(X:S)) -> TOP(proper(X:S)) 72.14/72.29 TOP(ok(X:S)) -> ACTIVE(X:S) 72.14/72.29 TOP(ok(X:S)) -> TOP(active(X:S)) 72.14/72.29 -> Rules: 72.14/72.29 active(g(X:S)) -> mark(h(X:S)) 72.14/72.29 active(h(d)) -> mark(g(c)) 72.14/72.29 active(c) -> mark(d) 72.14/72.29 g(ok(X:S)) -> ok(g(X:S)) 72.14/72.29 h(ok(X:S)) -> ok(h(X:S)) 72.14/72.29 proper(g(X:S)) -> g(proper(X:S)) 72.14/72.29 proper(h(X:S)) -> h(proper(X:S)) 72.14/72.29 proper(c) -> ok(c) 72.14/72.29 proper(d) -> ok(d) 72.14/72.29 top(mark(X:S)) -> top(proper(X:S)) 72.14/72.29 top(ok(X:S)) -> top(active(X:S)) 72.14/72.29 ->Strongly Connected Components: 72.14/72.29 ->->Cycle: 72.14/72.29 ->->-> Pairs: 72.14/72.29 H(ok(X:S)) -> H(X:S) 72.14/72.29 ->->-> Rules: 72.14/72.29 active(g(X:S)) -> mark(h(X:S)) 72.14/72.29 active(h(d)) -> mark(g(c)) 72.14/72.29 active(c) -> mark(d) 72.14/72.29 g(ok(X:S)) -> ok(g(X:S)) 72.14/72.29 h(ok(X:S)) -> ok(h(X:S)) 72.14/72.29 proper(g(X:S)) -> g(proper(X:S)) 72.14/72.29 proper(h(X:S)) -> h(proper(X:S)) 72.14/72.29 proper(c) -> ok(c) 72.14/72.29 proper(d) -> ok(d) 72.14/72.29 top(mark(X:S)) -> top(proper(X:S)) 72.14/72.29 top(ok(X:S)) -> top(active(X:S)) 72.14/72.29 ->->Cycle: 72.14/72.29 ->->-> Pairs: 72.14/72.29 G(ok(X:S)) -> G(X:S) 72.14/72.29 ->->-> Rules: 72.14/72.29 active(g(X:S)) -> mark(h(X:S)) 72.14/72.29 active(h(d)) -> mark(g(c)) 72.14/72.29 active(c) -> mark(d) 72.14/72.29 g(ok(X:S)) -> ok(g(X:S)) 72.14/72.29 h(ok(X:S)) -> ok(h(X:S)) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS_Innermost 2019-03-28 22.12