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Integer_Transition_Systems 2019-03-29 01.54 pair #432273299
details
property
value
status
complete
benchmark
whileNestedOffset_rec.jar-obl-9.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n166.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
30.4259 seconds
cpu usage
30.3414
user time
28.7497
system time
1.59167
max virtual memory
974128.0
max residence set size
283088.0
stage attributes
key
value
starexec-result
NO
output
30.24/30.42 NO 30.24/30.42 30.24/30.42 Solver Timeout: 4 30.24/30.42 Global Timeout: 300 30.24/30.42 No parsing errors! 30.24/30.42 Init Location: 0 30.24/30.42 Transitions: 30.24/30.42 <l0, l4, true> 30.24/30.42 <l1, l2, (arg1 > 0) /\ (arg2 > ~(1)), par{arg1 -> arg2, arg2 -> undef2}> 30.24/30.42 <l2, l2, (arg1 > ~(1)) /\ (arg1 < 10) /\ ((arg1 + 1) > arg1), par{arg1 -> (arg1 + 1), arg2 -> undef4}> 30.24/30.42 <l2, l3, (arg1 < 10), par{arg2 -> undef6}> 30.24/30.42 <l3, l3, (arg1 > 5) /\ ((arg1 + 1) > arg1), par{arg1 -> (arg1 + 1), arg2 -> undef8}> 30.24/30.42 <l4, l1, true, par{arg1 -> undef9, arg2 -> undef10}> 30.24/30.42 30.24/30.42 Fresh variables: 30.24/30.42 undef2, undef4, undef6, undef8, undef9, undef10, 30.24/30.42 30.24/30.42 Undef variables: 30.24/30.42 undef2, undef4, undef6, undef8, undef9, undef10, 30.24/30.42 30.24/30.42 Abstraction variables: 30.24/30.42 30.24/30.42 Exit nodes: 30.24/30.42 30.24/30.42 Accepting locations: 30.24/30.42 30.24/30.42 Asserts: 30.24/30.42 30.24/30.42 Preprocessed LLVMGraph 30.24/30.42 Init Location: 0 30.24/30.42 Transitions: 30.24/30.42 <l0, l2, (arg1 = undef10) /\ (undef9 > 0) /\ (undef10 > ~(1))> 30.24/30.42 <l2, l2, (arg1 > ~(1)) /\ (arg1 < 10) /\ ((arg1 + 1) > arg1), par{arg1 -> (arg1 + 1)}> 30.24/30.42 <l2, l3, (arg1 < 10)> 30.24/30.42 <l3, l3, (arg1 > 5) /\ ((arg1 + 1) > arg1), par{arg1 -> (arg1 + 1)}> 30.24/30.42 30.24/30.42 Fresh variables: 30.24/30.42 undef2, undef4, undef6, undef8, undef9, undef10, 30.24/30.42 30.24/30.42 Undef variables: 30.24/30.42 undef2, undef4, undef6, undef8, undef9, undef10, 30.24/30.42 30.24/30.42 Abstraction variables: 30.24/30.42 30.24/30.42 Exit nodes: 30.24/30.42 30.24/30.42 Accepting locations: 30.24/30.42 30.24/30.42 Asserts: 30.24/30.42 30.24/30.42 ************************************************************* 30.24/30.42 ******************************************************************************************* 30.24/30.42 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 30.24/30.42 ******************************************************************************************* 30.24/30.42 30.24/30.42 Init Location: 0 30.24/30.42 Graph 0: 30.24/30.42 Transitions: 30.24/30.42 Variables: 30.24/30.42 30.24/30.42 Graph 1: 30.24/30.42 Transitions: 30.24/30.42 <l2, l2, 0 <= arg1 /\ arg1 <= 9, {arg1 -> 1 + arg1, rest remain the same}> 30.24/30.42 Variables: 30.24/30.42 arg1 30.24/30.42 30.24/30.42 Graph 2: 30.24/30.42 Transitions: 30.24/30.42 <l3, l3, 6 <= arg1, {arg1 -> 1 + arg1, rest remain the same}> 30.24/30.42 Variables: 30.24/30.42 arg1 30.24/30.42 30.24/30.42 Precedence: 30.24/30.42 Graph 0 30.24/30.42 30.24/30.42 Graph 1 30.24/30.42 <l0, l2, 0 <= undef10 /\ 1 <= undef9 /\ arg1 = undef10, {all remain the same}> 30.24/30.42 30.24/30.42 Graph 2 30.24/30.42 <l2, l3, arg1 <= 9, {all remain the same}> 30.24/30.42 30.24/30.42 Map Locations to Subgraph: 30.24/30.42 ( 0 , 0 ) 30.24/30.42 ( 2 , 1 ) 30.24/30.42 ( 3 , 2 ) 30.24/30.42 30.24/30.42 ******************************************************************************************* 30.24/30.42 ******************************** CHECKING ASSERTIONS ******************************** 30.24/30.42 ******************************************************************************************* 30.24/30.42 30.24/30.42 Proving termination of subgraph 0 30.24/30.42 Proving termination of subgraph 1 30.24/30.42 Checking unfeasibility... 30.24/30.42 Time used: 0.00165 30.24/30.42 30.24/30.42 Checking conditional termination of SCC {l2}... 30.24/30.42 30.24/30.42 LOG: CALL solveLinear 30.24/30.42 30.24/30.42 LOG: RETURN solveLinear - Elapsed time: 0.000592s
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