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Integer_Transition_Systems 2019-03-29 01.54 pair #432273467
details
property
value
status
complete
benchmark
complInterv3_rec.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n112.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
18.3377 seconds
cpu usage
18.284
user time
17.1089
system time
1.1751
max virtual memory
942084.0
max residence set size
240448.0
stage attributes
key
value
starexec-result
NO
output
18.26/18.33 NO 18.26/18.33 18.26/18.33 Solver Timeout: 4 18.26/18.33 Global Timeout: 300 18.26/18.33 No parsing errors! 18.26/18.33 Init Location: 0 18.26/18.33 Transitions: 18.26/18.33 <l0, l3, true> 18.26/18.33 <l1, l2, (arg1 > 0) /\ (arg2 > ~(1)), par{arg1 -> arg2, arg2 -> undef2}> 18.26/18.33 <l2, l2, (arg1 > 5), par{arg1 -> (arg1 + 1), arg2 -> undef4}> 18.26/18.33 <l2, l2, (arg1 > 0) /\ (arg1 < 6), par{arg1 -> 0, arg2 -> undef6}> 18.26/18.33 <l3, l1, true, par{arg1 -> undef7, arg2 -> undef8}> 18.26/18.33 18.26/18.33 Fresh variables: 18.26/18.33 undef2, undef4, undef6, undef7, undef8, 18.26/18.33 18.26/18.33 Undef variables: 18.26/18.33 undef2, undef4, undef6, undef7, undef8, 18.26/18.33 18.26/18.33 Abstraction variables: 18.26/18.33 18.26/18.33 Exit nodes: 18.26/18.33 18.26/18.33 Accepting locations: 18.26/18.33 18.26/18.33 Asserts: 18.26/18.33 18.26/18.33 Preprocessed LLVMGraph 18.26/18.33 Init Location: 0 18.26/18.33 Transitions: 18.26/18.33 <l0, l2, (arg1 = undef8) /\ (undef7 > 0) /\ (undef8 > ~(1))> 18.26/18.33 <l2, l2, (arg1 > 5), par{arg1 -> (arg1 + 1)}> 18.26/18.33 <l2, l2, (arg1 > 0) /\ (arg1 < 6), par{arg1 -> 0}> 18.26/18.33 18.26/18.33 Fresh variables: 18.26/18.33 undef2, undef4, undef6, undef7, undef8, 18.26/18.33 18.26/18.33 Undef variables: 18.26/18.33 undef2, undef4, undef6, undef7, undef8, 18.26/18.33 18.26/18.33 Abstraction variables: 18.26/18.33 18.26/18.33 Exit nodes: 18.26/18.33 18.26/18.33 Accepting locations: 18.26/18.33 18.26/18.33 Asserts: 18.26/18.33 18.26/18.33 ************************************************************* 18.26/18.33 ******************************************************************************************* 18.26/18.33 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 18.26/18.33 ******************************************************************************************* 18.26/18.33 18.26/18.33 Init Location: 0 18.26/18.33 Graph 0: 18.26/18.33 Transitions: 18.26/18.33 Variables: 18.26/18.33 18.26/18.33 Graph 1: 18.26/18.33 Transitions: 18.26/18.33 <l2, l2, 6 <= arg1, {arg1 -> 1 + arg1, rest remain the same}> 18.26/18.33 <l2, l2, 1 <= arg1 /\ arg1 <= 5, {arg1 -> 0, rest remain the same}> 18.26/18.33 Variables: 18.26/18.33 arg1 18.26/18.33 18.26/18.33 Precedence: 18.26/18.33 Graph 0 18.26/18.33 18.26/18.33 Graph 1 18.26/18.33 <l0, l2, 0 <= undef8 /\ 1 <= undef7 /\ arg1 = undef8, {all remain the same}> 18.26/18.33 18.26/18.33 Map Locations to Subgraph: 18.26/18.33 ( 0 , 0 ) 18.26/18.33 ( 2 , 1 ) 18.26/18.33 18.26/18.33 ******************************************************************************************* 18.26/18.33 ******************************** CHECKING ASSERTIONS ******************************** 18.26/18.33 ******************************************************************************************* 18.26/18.33 18.26/18.33 Proving termination of subgraph 0 18.26/18.33 Proving termination of subgraph 1 18.26/18.33 Checking unfeasibility... 18.26/18.33 Time used: 0.00293 18.26/18.33 18.26/18.33 Checking conditional termination of SCC {l2}... 18.26/18.33 18.26/18.33 LOG: CALL solveLinear 18.26/18.33 18.26/18.33 LOG: RETURN solveLinear - Elapsed time: 0.000737s 18.26/18.33 18.26/18.33 LOG: CALL solveLinear 18.26/18.33 18.26/18.33 LOG: RETURN solveLinear - Elapsed time: 0.003420s 18.26/18.33 �[33mPiecewise ranking function: �[36mmin(-7 + 7*arg1,71 - 6*arg1)�[0m 18.26/18.33 New Graphs: 18.26/18.33 Transitions: 18.26/18.33 <l2, l2, 6 <= arg1, {arg1 -> 1 + arg1, rest remain the same}> 18.26/18.33 Variables: 18.26/18.33 arg1 18.26/18.33 Checking conditional termination of SCC {l2}...
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