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Integer_Transition_Systems 2019-03-29 01.54 pair #432274088
details
property
value
status
complete
benchmark
n-16a.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n134.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
5.26819 seconds
cpu usage
5.26814
user time
5.00315
system time
0.264985
max virtual memory
720792.0
max residence set size
64840.0
stage attributes
key
value
starexec-result
NO
output
5.22/5.26 NO 5.22/5.26 5.22/5.26 Solver Timeout: 4 5.22/5.26 Global Timeout: 300 5.22/5.26 No parsing errors! 5.22/5.26 Init Location: 0 5.22/5.26 Transitions: 5.22/5.26 <l0, l5, true> 5.22/5.26 <l1, l2, true> 5.22/5.26 <l2, l3, (undef5 = ((0 + x_5^0) + y_6^0)) /\ ((0 + (~(1) * undef5)) <= 0), par{x_5^0 -> undef5}> 5.22/5.26 <l3, l2, true> 5.22/5.26 <l2, l4, (undef11 = ((0 + x_5^0) + y_6^0)) /\ (0 <= (~(1) + (~(1) * undef11))) /\ (undef10 = undef10), par{Result_4^0 -> undef10, x_5^0 -> undef11}> 5.22/5.26 <l5, l1, true> 5.22/5.26 5.22/5.26 Fresh variables: 5.22/5.26 undef5, undef10, undef11, 5.22/5.26 5.22/5.26 Undef variables: 5.22/5.26 undef5, undef10, undef11, 5.22/5.26 5.22/5.26 Abstraction variables: 5.22/5.26 5.22/5.26 Exit nodes: 5.22/5.26 5.22/5.26 Accepting locations: 5.22/5.26 5.22/5.26 Asserts: 5.22/5.26 5.22/5.26 Preprocessed LLVMGraph 5.22/5.26 Init Location: 0 5.22/5.26 Transitions: 5.22/5.26 <l0, l2, true> 5.22/5.26 <l2, l2, (undef5 = ((0 + x_5^0) + y_6^0)) /\ ((0 + (~(1) * undef5)) <= 0), par{x_5^0 -> undef5}> 5.22/5.26 <l2, l4, (undef11 = ((0 + x_5^0) + y_6^0)) /\ (0 <= (~(1) + (~(1) * undef11))) /\ (undef10 = undef10), par{x_5^0 -> undef11}> 5.22/5.26 5.22/5.26 Fresh variables: 5.22/5.26 undef5, undef10, undef11, 5.22/5.26 5.22/5.26 Undef variables: 5.22/5.26 undef5, undef10, undef11, 5.22/5.26 5.22/5.26 Abstraction variables: 5.22/5.26 5.22/5.26 Exit nodes: 5.22/5.26 5.22/5.26 Accepting locations: 5.22/5.26 5.22/5.26 Asserts: 5.22/5.26 5.22/5.26 ************************************************************* 5.22/5.26 ******************************************************************************************* 5.22/5.26 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 5.22/5.26 ******************************************************************************************* 5.22/5.26 5.22/5.26 Init Location: 0 5.22/5.26 Graph 0: 5.22/5.26 Transitions: 5.22/5.26 Variables: 5.22/5.26 5.22/5.26 Graph 1: 5.22/5.26 Transitions: 5.22/5.26 <l2, l2, 0 <= undef5 /\ x_5^0 + y_6^0 = undef5, {x_5^0 -> undef5, rest remain the same}> 5.22/5.26 Variables: 5.22/5.26 x_5^0, y_6^0 5.22/5.26 5.22/5.26 Graph 2: 5.22/5.26 Transitions: 5.22/5.26 Variables: 5.22/5.26 5.22/5.26 Precedence: 5.22/5.26 Graph 0 5.22/5.26 5.22/5.26 Graph 1 5.22/5.26 <l0, l2, true, {all remain the same}> 5.22/5.26 5.22/5.26 Graph 2 5.22/5.26 <l2, l4, 1 + undef11 <= 0 /\ x_5^0 + y_6^0 = undef11, {x_5^0 -> undef11, rest remain the same}> 5.22/5.26 5.22/5.26 Map Locations to Subgraph: 5.22/5.26 ( 0 , 0 ) 5.22/5.26 ( 2 , 1 ) 5.22/5.26 ( 4 , 2 ) 5.22/5.26 5.22/5.26 ******************************************************************************************* 5.22/5.26 ******************************** CHECKING ASSERTIONS ******************************** 5.22/5.26 ******************************************************************************************* 5.22/5.26 5.22/5.26 Proving termination of subgraph 0 5.22/5.26 Proving termination of subgraph 1 5.22/5.26 Checking unfeasibility... 5.22/5.26 Time used: 0.001855 5.22/5.26 5.22/5.26 Checking conditional termination of SCC {l2}... 5.22/5.26 5.22/5.26 LOG: CALL solveLinear 5.22/5.26 5.22/5.26 LOG: RETURN solveLinear - Elapsed time: 0.000534s 5.22/5.26 5.22/5.26 LOG: CALL solveLinear 5.22/5.26
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