details

property	value
status	complete
benchmark	smagillb-succeed.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n157.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp2019_ITS
runtime (wallclock)	18.3247 seconds
cpu usage	18.2773
user time	17.1764
system time	1.10093
max virtual memory	969308.0
max residence set size	262116.0

stage attributes

key	value
starexec-result	NO

output

18.26/18.32 NO 18.26/18.32 18.26/18.32 Solver Timeout: 4 18.26/18.32 Global Timeout: 300 18.26/18.32 No parsing errors! 18.26/18.32 Init Location: 0 18.26/18.32 Transitions: 18.26/18.32 <l0, l9, true> 18.26/18.32 <l1, l2, true> 18.26/18.32 <l3, l4, true> 18.26/18.32 <l5, l6, true> 18.26/18.32 <l6, l5, true> 18.26/18.32 <l7, l1, ((0 + __rho_1_^0) <= 0) /\ ((1 + c^0) <= (0 + curr_serv^0)), par{curr_serv^0 -> (~(1) + curr_serv^0)}> 18.26/18.32 <l7, l1, (1 <= (0 + __rho_1_^0)), par{c^0 -> (~(1) + c^0), curr_serv^0 -> (~(1) + curr_serv^0), resp^0 -> (1 + resp^0)}> 18.26/18.32 <l2, l7, (1 <= (0 + curr_serv^0)) /\ (undef43 = undef43), par{__rho_1_^0 -> undef43}> 18.26/18.32 <l2, l5, ((0 + curr_serv^0) <= 0)> 18.26/18.32 <l8, l1, (undef63 = undef63) /\ (undef58 = (0 + undef63)) /\ (1 <= (0 + undef58)) /\ (undef61 = undef61) /\ (1 <= (0 + undef61)) /\ (undef62 = undef62) /\ ((1 + (2 * undef62)) <= (0 + undef61)) /\ ((0 + undef61) <= (1 + (2 * undef62))), par{c^0 -> undef58, curr_serv^0 -> (0 + undef61), resp^0 -> 0, servers^0 -> undef61, serversdiv2^0 -> undef62, tmp1^0 -> undef63}> 18.26/18.32 <l9, l8, true> 18.26/18.32 18.26/18.32 Fresh variables: 18.26/18.32 undef43, undef58, undef61, undef62, undef63, 18.26/18.32 18.26/18.32 Undef variables: 18.26/18.32 undef43, undef58, undef61, undef62, undef63, 18.26/18.32 18.26/18.32 Abstraction variables: 18.26/18.32 18.26/18.32 Exit nodes: 18.26/18.32 18.26/18.32 Accepting locations: 18.26/18.32 18.26/18.32 Asserts: 18.26/18.32 18.26/18.32 Preprocessed LLVMGraph 18.26/18.32 Init Location: 0 18.26/18.32 Transitions: 18.26/18.32 <l0, l1, (c^0 = undef58) /\ (curr_serv^0 = (0 + undef61)) /\ (resp^0 = 0) /\ (undef63 = undef63) /\ (undef58 = (0 + undef63)) /\ (1 <= (0 + undef58)) /\ (undef61 = undef61) /\ (1 <= (0 + undef61)) /\ (undef62 = undef62) /\ ((1 + (2 * undef62)) <= (0 + undef61)) /\ ((0 + undef61) <= (1 + (2 * undef62)))> 18.26/18.32 <l1, l1, (1 <= (0 + curr_serv^0)) /\ (undef43 = undef43) /\ ((0 + undef43) <= 0) /\ ((1 + c^0) <= (0 + curr_serv^0)), par{curr_serv^0 -> (~(1) + curr_serv^0)}> 18.26/18.32 <l1, l1, (1 <= (0 + curr_serv^0)) /\ (undef43 = undef43) /\ (1 <= (0 + undef43)), par{c^0 -> (~(1) + c^0), curr_serv^0 -> (~(1) + curr_serv^0), resp^0 -> (1 + resp^0)}> 18.26/18.32 <l1, l5, ((0 + curr_serv^0) <= 0)> 18.26/18.32 <l5, l5, true> 18.26/18.32 18.26/18.32 Fresh variables: 18.26/18.32 undef43, undef58, undef61, undef62, undef63, 18.26/18.32 18.26/18.32 Undef variables: 18.26/18.32 undef43, undef58, undef61, undef62, undef63, 18.26/18.32 18.26/18.32 Abstraction variables: 18.26/18.32 18.26/18.32 Exit nodes: 18.26/18.32 18.26/18.32 Accepting locations: 18.26/18.32 18.26/18.32 Asserts: 18.26/18.32 18.26/18.32 ************************************************************* 18.26/18.32 ******************************************************************************************* 18.26/18.32 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 18.26/18.32 ******************************************************************************************* 18.26/18.32 18.26/18.32 Init Location: 0 18.26/18.32 Graph 0: 18.26/18.32 Transitions: 18.26/18.32 Variables: 18.26/18.32 18.26/18.32 Graph 1: 18.26/18.32 Transitions: 18.26/18.32 <l1, l1, undef43 <= 0 /\ 1 + c^0 <= curr_serv^0 /\ 1 <= curr_serv^0, {curr_serv^0 -> -1 + curr_serv^0, rest remain the same}> 18.26/18.32 <l1, l1, 1 <= curr_serv^0 /\ 1 <= undef43, {c^0 -> -1 + c^0, curr_serv^0 -> -1 + curr_serv^0, resp^0 -> 1 + resp^0, rest remain the same}> 18.26/18.32 Variables: 18.26/18.32 c^0, curr_serv^0, resp^0 18.26/18.32 18.26/18.32 Graph 2: 18.26/18.32 Transitions: 18.26/18.32 <l5, l5, true, {all remain the same}> 18.26/18.32 Variables: 18.26/18.32 18.26/18.32 Precedence: 18.26/18.32 Graph 0 18.26/18.32 18.26/18.32 Graph 1 18.26/18.32 <l0, l1, 1 <= undef58 /\ 1 <= undef61 /\ c^0 = undef58 /\ curr_serv^0 = undef61 /\ resp^0 = 0 /\ undef58 = undef63 /\ undef61 = 1 + 2*undef62, {all remain the same}> 18.26/18.32 18.26/18.32 Graph 2 18.26/18.32 <l1, l5, curr_serv^0 <= 0, {all remain the same}> 18.26/18.32 18.26/18.32 Map Locations to Subgraph: 18.26/18.32 ( 0 , 0 ) 18.26/18.32 ( 1 , 1 ) 18.26/18.32 ( 5 , 2 ) 18.26/18.32 18.26/18.32 ******************************************************************************************* 18.26/18.32 ******************************** CHECKING ASSERTIONS ******************************** 18.26/18.32 ******************************************************************************************* 18.26/18.32 18.26/18.32 Proving termination of subgraph 0 18.26/18.32 Proving termination of subgraph 1 18.26/18.32 Checking unfeasibility... 18.26/18.32 Time used: 0.006002 popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to Integer_Transition_Systems 2019-03-29 01.54