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Integer_Transition_Systems 2019-03-29 01.54 pair #432274601
details
property
value
status
complete
benchmark
n-18.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n008.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
18.2657 seconds
cpu usage
18.2486
user time
17.0989
system time
1.14971
max virtual memory
919204.0
max residence set size
226752.0
stage attributes
key
value
starexec-result
NO
output
18.20/18.26 NO 18.20/18.26 18.20/18.26 Solver Timeout: 4 18.20/18.26 Global Timeout: 300 18.20/18.26 No parsing errors! 18.20/18.26 Init Location: 0 18.20/18.26 Transitions: 18.20/18.26 <l0, l5, true> 18.20/18.26 <l1, l2, true> 18.20/18.26 <l2, l3, (undef4 = (~(1) + x_5^0)) /\ ((0 + undef4) <= 0), par{x_5^0 -> undef4}> 18.20/18.26 <l3, l2, true> 18.20/18.26 <l2, l4, (undef8 = (~(1) + x_5^0)) /\ (0 <= (~(1) + undef8)) /\ (undef7 = undef7), par{Result_4^0 -> undef7, x_5^0 -> undef8}> 18.20/18.26 <l5, l1, true> 18.20/18.26 18.20/18.26 Fresh variables: 18.20/18.26 undef4, undef7, undef8, 18.20/18.26 18.20/18.26 Undef variables: 18.20/18.26 undef4, undef7, undef8, 18.20/18.26 18.20/18.26 Abstraction variables: 18.20/18.26 18.20/18.26 Exit nodes: 18.20/18.26 18.20/18.26 Accepting locations: 18.20/18.26 18.20/18.26 Asserts: 18.20/18.26 18.20/18.26 Preprocessed LLVMGraph 18.20/18.26 Init Location: 0 18.20/18.26 Transitions: 18.20/18.26 <l0, l2, true> 18.20/18.26 <l2, l2, (undef4 = (~(1) + x_5^0)) /\ ((0 + undef4) <= 0), par{x_5^0 -> undef4}> 18.20/18.26 <l2, l4, (undef8 = (~(1) + x_5^0)) /\ (0 <= (~(1) + undef8)) /\ (undef7 = undef7), par{x_5^0 -> undef8}> 18.20/18.26 18.20/18.26 Fresh variables: 18.20/18.26 undef4, undef7, undef8, 18.20/18.26 18.20/18.26 Undef variables: 18.20/18.26 undef4, undef7, undef8, 18.20/18.26 18.20/18.26 Abstraction variables: 18.20/18.26 18.20/18.26 Exit nodes: 18.20/18.26 18.20/18.26 Accepting locations: 18.20/18.26 18.20/18.26 Asserts: 18.20/18.26 18.20/18.26 ************************************************************* 18.20/18.26 ******************************************************************************************* 18.20/18.26 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 18.20/18.26 ******************************************************************************************* 18.20/18.26 18.20/18.26 Init Location: 0 18.20/18.26 Graph 0: 18.20/18.26 Transitions: 18.20/18.26 Variables: 18.20/18.26 18.20/18.26 Graph 1: 18.20/18.26 Transitions: 18.20/18.26 <l2, l2, undef4 <= 0 /\ x_5^0 = 1 + undef4, {x_5^0 -> undef4, rest remain the same}> 18.20/18.26 Variables: 18.20/18.26 x_5^0 18.20/18.26 18.20/18.26 Graph 2: 18.20/18.26 Transitions: 18.20/18.26 Variables: 18.20/18.26 18.20/18.26 Precedence: 18.20/18.26 Graph 0 18.20/18.26 18.20/18.26 Graph 1 18.20/18.26 <l0, l2, true, {all remain the same}> 18.20/18.26 18.20/18.26 Graph 2 18.20/18.26 <l2, l4, 1 <= undef8 /\ x_5^0 = 1 + undef8, {x_5^0 -> undef8, rest remain the same}> 18.20/18.26 18.20/18.26 Map Locations to Subgraph: 18.20/18.26 ( 0 , 0 ) 18.20/18.26 ( 2 , 1 ) 18.20/18.26 ( 4 , 2 ) 18.20/18.26 18.20/18.26 ******************************************************************************************* 18.20/18.26 ******************************** CHECKING ASSERTIONS ******************************** 18.20/18.26 ******************************************************************************************* 18.20/18.26 18.20/18.26 Proving termination of subgraph 0 18.20/18.26 Proving termination of subgraph 1 18.20/18.26 Checking unfeasibility... 18.20/18.26 Time used: 0.001483 18.20/18.26 18.20/18.26 Checking conditional termination of SCC {l2}... 18.20/18.26 18.20/18.26 LOG: CALL solveLinear 18.20/18.26 18.20/18.26 LOG: RETURN solveLinear - Elapsed time: 0.000529s 18.20/18.26 18.20/18.26 LOG: CALL solveLinear 18.20/18.26
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