Integer_Transition_Systems 2019-03-29 01.54 pair #432274725

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details
property value
status timeout (wallclock)
benchmark reverse_seg_cyclic.t2.smt2
ran by Akihisa Yamada
cpu timeout 1200 seconds
wallclock timeout 300 seconds
memory limit 137438953472 bytes
space From_T2
run statistics
property value
solver Ctrl
configuration Transition
runtime (wallclock) 300.037 seconds
cpu usage 303.436
user time 185.73
system time 117.706
max virtual memory 882940.0
max residence set size 162456.0
stage attributes

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