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Integer_Transition_Systems 2019-03-29 01.54 pair #432274958
details
property
value
status
complete
benchmark
n-37.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n013.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
43.4273 seconds
cpu usage
43.3617
user time
41.2673
system time
2.09439
max virtual memory
955840.0
max residence set size
286772.0
stage attributes
key
value
starexec-result
NO
output
43.32/43.42 NO 43.32/43.42 43.32/43.42 Solver Timeout: 4 43.32/43.42 Global Timeout: 300 43.32/43.42 No parsing errors! 43.32/43.42 Init Location: 0 43.32/43.42 Transitions: 43.32/43.42 <l0, l7, true> 43.32/43.42 <l1, l2, (undef2 = (0 + x_5^0)) /\ (undef8 = (0 + undef2)) /\ (undef1 = undef1), par{Result_4^0 -> undef1, __cil_tmp2_6^0 -> undef2, selected_11^0 -> (0 + undef8)}> 43.32/43.42 <l3, l2, (undef10 = (0 + x_5^0)) /\ (undef16 = (0 + undef10)) /\ (undef9 = undef9), par{Result_4^0 -> undef9, __cil_tmp2_6^0 -> undef10, selected_11^0 -> (0 + undef16)}> 43.32/43.42 <l4, l5, (undef19 = (0 + selected_11^0)), par{Result_4^0 -> (0 + undef19), __cil_tmp6_12^0 -> undef19}> 43.32/43.42 <l4, l2, (undef25 = (0 + x_5^0)) /\ (undef31 = (0 + undef25)) /\ (undef24 = undef24), par{Result_4^0 -> undef24, __cil_tmp2_6^0 -> undef25, selected_11^0 -> (0 + undef31)}> 43.32/43.42 <l2, l4, true, par{retryCount_10^0 -> (1 + retryCount_10^0)}> 43.32/43.42 <l6, l4, true, par{maxRetries_9^0 -> 4, retryCount_10^0 -> 0, selected_11^0 -> 0}> 43.32/43.42 <l7, l6, true> 43.32/43.42 43.32/43.42 Fresh variables: 43.32/43.42 undef1, undef2, undef8, undef9, undef10, undef16, undef19, undef24, undef25, undef31, 43.32/43.42 43.32/43.42 Undef variables: 43.32/43.42 undef1, undef2, undef8, undef9, undef10, undef16, undef19, undef24, undef25, undef31, 43.32/43.42 43.32/43.42 Abstraction variables: 43.32/43.42 43.32/43.42 Exit nodes: 43.32/43.42 43.32/43.42 Accepting locations: 43.32/43.42 43.32/43.42 Asserts: 43.32/43.42 43.32/43.42 Preprocessed LLVMGraph 43.32/43.42 Init Location: 0 43.32/43.42 Transitions: 43.32/43.42 <l0, l4, (retryCount_10^0 = 0) /\ (selected_11^0 = 0)> 43.32/43.42 <l4, l5, (undef19 = (0 + selected_11^0))> 43.32/43.42 <l4, l4, (undef25 = (0 + x_5^0)) /\ (undef31 = (0 + undef25)) /\ (undef24 = undef24), par{retryCount_10^0 -> (1 + retryCount_10^0), selected_11^0 -> (0 + undef31)}> 43.32/43.42 43.32/43.42 Fresh variables: 43.32/43.42 undef1, undef2, undef8, undef9, undef10, undef16, undef19, undef24, undef25, undef31, 43.32/43.42 43.32/43.42 Undef variables: 43.32/43.42 undef1, undef2, undef8, undef9, undef10, undef16, undef19, undef24, undef25, undef31, 43.32/43.42 43.32/43.42 Abstraction variables: 43.32/43.42 43.32/43.42 Exit nodes: 43.32/43.42 43.32/43.42 Accepting locations: 43.32/43.42 43.32/43.42 Asserts: 43.32/43.42 43.32/43.42 ************************************************************* 43.32/43.42 ******************************************************************************************* 43.32/43.42 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 43.32/43.42 ******************************************************************************************* 43.32/43.42 43.32/43.42 Init Location: 0 43.32/43.42 Graph 0: 43.32/43.42 Transitions: 43.32/43.42 Variables: 43.32/43.42 43.32/43.42 Graph 1: 43.32/43.42 Transitions: 43.32/43.42 <l4, l4, x_5^0 = undef25 /\ undef25 = undef31, {retryCount_10^0 -> 1 + retryCount_10^0, selected_11^0 -> undef31, rest remain the same}> 43.32/43.42 Variables: 43.32/43.42 retryCount_10^0, selected_11^0, x_5^0 43.32/43.42 43.32/43.42 Graph 2: 43.32/43.42 Transitions: 43.32/43.42 Variables: 43.32/43.42 43.32/43.42 Precedence: 43.32/43.42 Graph 0 43.32/43.42 43.32/43.42 Graph 1 43.32/43.42 <l0, l4, retryCount_10^0 = 0 /\ selected_11^0 = 0, {all remain the same}> 43.32/43.42 43.32/43.42 Graph 2 43.32/43.42 <l4, l5, selected_11^0 = undef19, {all remain the same}> 43.32/43.42 43.32/43.42 Map Locations to Subgraph: 43.32/43.42 ( 0 , 0 ) 43.32/43.42 ( 4 , 1 ) 43.32/43.42 ( 5 , 2 ) 43.32/43.42 43.32/43.42 ******************************************************************************************* 43.32/43.42 ******************************** CHECKING ASSERTIONS ******************************** 43.32/43.42 ******************************************************************************************* 43.32/43.42 43.32/43.42 Proving termination of subgraph 0 43.32/43.42 Proving termination of subgraph 1 43.32/43.42 Checking unfeasibility... 43.32/43.42 Time used: 0.002486 43.32/43.42 43.32/43.42 Checking conditional termination of SCC {l4}... 43.32/43.42 43.32/43.42 LOG: CALL solveLinear 43.32/43.42 43.32/43.42 LOG: RETURN solveLinear - Elapsed time: 0.000837s 43.32/43.42
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