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Integer_Transition_Systems 2019-03-29 01.54 pair #432274967
details
property
value
status
complete
benchmark
test_byron_2.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n168.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
5.06914 seconds
cpu usage
5.06909
user time
4.83257
system time
0.236524
max virtual memory
720140.0
max residence set size
56036.0
stage attributes
key
value
starexec-result
NO
output
5.02/5.06 NO 5.02/5.06 5.02/5.06 Solver Timeout: 4 5.02/5.06 Global Timeout: 300 5.02/5.06 No parsing errors! 5.02/5.06 Init Location: 0 5.02/5.06 Transitions: 5.02/5.06 <l0, l6, true> 5.02/5.06 <l1, l2, true> 5.02/5.06 <l2, l1, true> 5.02/5.06 <l3, l1, ((0 + n^0) <= 0) /\ (undef7 = 0), par{x^0 -> 1}> 5.02/5.06 <l3, l4, (1 <= (0 + n^0))> 5.02/5.06 <l4, l3, true> 5.02/5.06 <l5, l3, (undef12 = undef12), par{n^0 -> undef12, x^0 -> 1}> 5.02/5.06 <l6, l5, true> 5.02/5.06 5.02/5.06 Fresh variables: 5.02/5.06 undef7, undef12, 5.02/5.06 5.02/5.06 Undef variables: 5.02/5.06 undef7, undef12, 5.02/5.06 5.02/5.06 Abstraction variables: 5.02/5.06 5.02/5.06 Exit nodes: 5.02/5.06 5.02/5.06 Accepting locations: 5.02/5.06 5.02/5.06 Asserts: 5.02/5.06 5.02/5.06 Preprocessed LLVMGraph 5.02/5.06 Init Location: 0 5.02/5.06 Transitions: 5.02/5.06 <l0, l3, (n^0 = undef12) /\ (undef12 = undef12)> 5.02/5.06 <l1, l1, true> 5.02/5.06 <l3, l1, ((0 + n^0) <= 0) /\ (undef7 = 0)> 5.02/5.06 <l3, l3, (1 <= (0 + n^0))> 5.02/5.06 5.02/5.06 Fresh variables: 5.02/5.06 undef7, undef12, 5.02/5.06 5.02/5.06 Undef variables: 5.02/5.06 undef7, undef12, 5.02/5.06 5.02/5.06 Abstraction variables: 5.02/5.06 5.02/5.06 Exit nodes: 5.02/5.06 5.02/5.06 Accepting locations: 5.02/5.06 5.02/5.06 Asserts: 5.02/5.06 5.02/5.06 ************************************************************* 5.02/5.06 ******************************************************************************************* 5.02/5.06 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 5.02/5.06 ******************************************************************************************* 5.02/5.06 5.02/5.06 Init Location: 0 5.02/5.06 Graph 0: 5.02/5.06 Transitions: 5.02/5.06 Variables: 5.02/5.06 5.02/5.06 Graph 1: 5.02/5.06 Transitions: 5.02/5.06 <l3, l3, 1 <= n^0, {all remain the same}> 5.02/5.06 Variables: 5.02/5.06 n^0 5.02/5.06 5.02/5.06 Graph 2: 5.02/5.06 Transitions: 5.02/5.06 <l1, l1, true, {all remain the same}> 5.02/5.06 Variables: 5.02/5.06 5.02/5.06 Precedence: 5.02/5.06 Graph 0 5.02/5.06 5.02/5.06 Graph 1 5.02/5.06 <l0, l3, n^0 = undef12, {all remain the same}> 5.02/5.06 5.02/5.06 Graph 2 5.02/5.06 <l3, l1, n^0 <= 0 /\ undef7 = 0, {all remain the same}> 5.02/5.06 5.02/5.06 Map Locations to Subgraph: 5.02/5.06 ( 0 , 0 ) 5.02/5.06 ( 1 , 2 ) 5.02/5.06 ( 3 , 1 ) 5.02/5.06 5.02/5.06 ******************************************************************************************* 5.02/5.06 ******************************** CHECKING ASSERTIONS ******************************** 5.02/5.06 ******************************************************************************************* 5.02/5.06 5.02/5.06 Proving termination of subgraph 0 5.02/5.06 Proving termination of subgraph 1 5.02/5.06 Checking unfeasibility... 5.02/5.06 Time used: 0.001545 5.02/5.06 5.02/5.06 > No variable changes in termination graph. 5.02/5.06 Checking conditional unfeasibility... 5.02/5.06 Calling Safety with literal n^0 <= 0 and entry <l3, l3, true, {all remain the same}> 5.02/5.06
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