details

property	value
status	complete
benchmark	n-12a.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n069.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp2019_ITS
runtime (wallclock)	5.13059 seconds
cpu usage	5.08957
user time	4.77773
system time	0.311838
max virtual memory	853152.0
max residence set size	156664.0

stage attributes

key	value
starexec-result	NO

output

5.06/5.12 NO 5.06/5.12 5.06/5.12 Solver Timeout: 4 5.06/5.12 Global Timeout: 300 5.06/5.12 No parsing errors! 5.06/5.12 Init Location: 0 5.06/5.12 Transitions: 5.06/5.12 <l0, l5, true> 5.06/5.12 <l1, l2, true> 5.06/5.12 <l2, l3, ((0 + (~(1) * x_5^0)) <= 0)> 5.06/5.12 <l3, l2, true> 5.06/5.12 <l2, l4, (0 <= (~(1) + (~(1) * x_5^0))) /\ (undef7 = undef7), par{Result_4^0 -> undef7}> 5.06/5.12 <l5, l1, true> 5.06/5.12 5.06/5.12 Fresh variables: 5.06/5.12 undef7, 5.06/5.12 5.06/5.12 Undef variables: 5.06/5.12 undef7, 5.06/5.12 5.06/5.12 Abstraction variables: 5.06/5.12 5.06/5.12 Exit nodes: 5.06/5.12 5.06/5.12 Accepting locations: 5.06/5.12 5.06/5.12 Asserts: 5.06/5.12 5.06/5.12 Preprocessed LLVMGraph 5.06/5.12 Init Location: 0 5.06/5.12 Transitions: 5.06/5.12 <l0, l2, true> 5.06/5.12 <l2, l2, ((0 + (~(1) * x_5^0)) <= 0)> 5.06/5.12 <l2, l4, (0 <= (~(1) + (~(1) * x_5^0))) /\ (undef7 = undef7)> 5.06/5.12 5.06/5.12 Fresh variables: 5.06/5.12 undef7, 5.06/5.12 5.06/5.12 Undef variables: 5.06/5.12 undef7, 5.06/5.12 5.06/5.12 Abstraction variables: 5.06/5.12 5.06/5.12 Exit nodes: 5.06/5.12 5.06/5.12 Accepting locations: 5.06/5.12 5.06/5.12 Asserts: 5.06/5.12 5.06/5.12 ************************************************************* 5.06/5.12 ******************************************************************************************* 5.06/5.12 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 5.06/5.12 ******************************************************************************************* 5.06/5.12 5.06/5.12 Init Location: 0 5.06/5.12 Graph 0: 5.06/5.12 Transitions: 5.06/5.12 Variables: 5.06/5.12 5.06/5.12 Graph 1: 5.06/5.12 Transitions: 5.06/5.12 <l2, l2, 0 <= x_5^0, {all remain the same}> 5.06/5.12 Variables: 5.06/5.12 x_5^0 5.06/5.12 5.06/5.12 Graph 2: 5.06/5.12 Transitions: 5.06/5.12 Variables: 5.06/5.12 5.06/5.12 Precedence: 5.06/5.12 Graph 0 5.06/5.12 5.06/5.12 Graph 1 5.06/5.12 <l0, l2, true, {all remain the same}> 5.06/5.12 5.06/5.12 Graph 2 5.06/5.12 <l2, l4, 1 + x_5^0 <= 0, {all remain the same}> 5.06/5.12 5.06/5.12 Map Locations to Subgraph: 5.06/5.12 ( 0 , 0 ) 5.06/5.12 ( 2 , 1 ) 5.06/5.12 ( 4 , 2 ) 5.06/5.12 5.06/5.12 ******************************************************************************************* 5.06/5.12 ******************************** CHECKING ASSERTIONS ******************************** 5.06/5.12 ******************************************************************************************* 5.06/5.12 5.06/5.12 Proving termination of subgraph 0 5.06/5.12 Proving termination of subgraph 1 5.06/5.12 Checking unfeasibility... 5.06/5.12 Time used: 0.001476 5.06/5.12 5.06/5.12 > No variable changes in termination graph. 5.06/5.12 Checking conditional unfeasibility... 5.06/5.12 Calling Safety with literal 1 + x_5^0 <= 0 and entry <l2, l2, true, {all remain the same}> 5.06/5.12 5.06/5.12 LOG: CALL check - Post:1 + x_5^0 <= 0 - Process 1 5.06/5.12 * Exit transition: <l2, l2, true, {all remain the same}> 5.06/5.12 * Postcondition : 1 + x_5^0 <= 0 5.06/5.12 Postcodition moved up: 1 + x_5^0 <= 0 popout

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job log

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actions

all output return to Integer_Transition_Systems 2019-03-29 01.54