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Integer_Transition_Systems 2019-03-29 01.54 pair #432276029
details
property
value
status
complete
benchmark
n-13.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n122.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
18.1624 seconds
cpu usage
18.1604
user time
17.6486
system time
0.511841
max virtual memory
918768.0
max residence set size
221188.0
stage attributes
key
value
starexec-result
NO
output
18.06/18.16 NO 18.06/18.16 18.06/18.16 Solver Timeout: 4 18.06/18.16 Global Timeout: 300 18.06/18.16 No parsing errors! 18.06/18.16 Init Location: 0 18.06/18.16 Transitions: 18.06/18.16 <l0, l5, true> 18.06/18.16 <l1, l2, true> 18.06/18.16 <l2, l3, ((0 + (~(1) * x_5^0)) <= 0), par{x_5^0 -> (1 + x_5^0)}> 18.06/18.16 <l3, l2, true> 18.06/18.16 <l2, l4, (0 <= (~(1) + (~(1) * x_5^0))) /\ (undef7 = undef7), par{Result_4^0 -> undef7}> 18.06/18.16 <l5, l1, true> 18.06/18.16 18.06/18.16 Fresh variables: 18.06/18.16 undef7, 18.06/18.16 18.06/18.16 Undef variables: 18.06/18.16 undef7, 18.06/18.16 18.06/18.16 Abstraction variables: 18.06/18.16 18.06/18.16 Exit nodes: 18.06/18.16 18.06/18.16 Accepting locations: 18.06/18.16 18.06/18.16 Asserts: 18.06/18.16 18.06/18.16 Preprocessed LLVMGraph 18.06/18.16 Init Location: 0 18.06/18.16 Transitions: 18.06/18.16 <l0, l2, true> 18.06/18.16 <l2, l2, ((0 + (~(1) * x_5^0)) <= 0), par{x_5^0 -> (1 + x_5^0)}> 18.06/18.16 <l2, l4, (0 <= (~(1) + (~(1) * x_5^0))) /\ (undef7 = undef7)> 18.06/18.16 18.06/18.16 Fresh variables: 18.06/18.16 undef7, 18.06/18.16 18.06/18.16 Undef variables: 18.06/18.16 undef7, 18.06/18.16 18.06/18.16 Abstraction variables: 18.06/18.16 18.06/18.16 Exit nodes: 18.06/18.16 18.06/18.16 Accepting locations: 18.06/18.16 18.06/18.16 Asserts: 18.06/18.16 18.06/18.16 ************************************************************* 18.06/18.16 ******************************************************************************************* 18.06/18.16 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 18.06/18.16 ******************************************************************************************* 18.06/18.16 18.06/18.16 Init Location: 0 18.06/18.16 Graph 0: 18.06/18.16 Transitions: 18.06/18.16 Variables: 18.06/18.16 18.06/18.16 Graph 1: 18.06/18.16 Transitions: 18.06/18.16 <l2, l2, 0 <= x_5^0, {x_5^0 -> 1 + x_5^0, rest remain the same}> 18.06/18.16 Variables: 18.06/18.16 x_5^0 18.06/18.16 18.06/18.16 Graph 2: 18.06/18.16 Transitions: 18.06/18.16 Variables: 18.06/18.16 18.06/18.16 Precedence: 18.06/18.16 Graph 0 18.06/18.16 18.06/18.16 Graph 1 18.06/18.16 <l0, l2, true, {all remain the same}> 18.06/18.16 18.06/18.16 Graph 2 18.06/18.16 <l2, l4, 1 + x_5^0 <= 0, {all remain the same}> 18.06/18.16 18.06/18.16 Map Locations to Subgraph: 18.06/18.16 ( 0 , 0 ) 18.06/18.16 ( 2 , 1 ) 18.06/18.16 ( 4 , 2 ) 18.06/18.16 18.06/18.16 ******************************************************************************************* 18.06/18.16 ******************************** CHECKING ASSERTIONS ******************************** 18.06/18.16 ******************************************************************************************* 18.06/18.16 18.06/18.16 Proving termination of subgraph 0 18.06/18.16 Proving termination of subgraph 1 18.06/18.16 Checking unfeasibility... 18.06/18.16 Time used: 0.00142 18.06/18.16 18.06/18.16 Checking conditional termination of SCC {l2}... 18.06/18.16 18.06/18.16 LOG: CALL solveLinear 18.06/18.16 18.06/18.16 LOG: RETURN solveLinear - Elapsed time: 0.000604s 18.06/18.16 18.06/18.16 LOG: CALL solveLinear 18.06/18.16
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