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Integer_Transition_Systems 2019-03-29 01.54 pair #432276350
details
property
value
status
complete
benchmark
ppblockterm.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n172.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp2019_ITS
runtime (wallclock)
127.314 seconds
cpu usage
127.071
user time
120.716
system time
6.35434
max virtual memory
1189960.0
max residence set size
422216.0
stage attributes
key
value
starexec-result
NO
output
127.03/127.30 NO 127.03/127.30 127.03/127.30 Solver Timeout: 4 127.03/127.30 Global Timeout: 300 127.03/127.30 No parsing errors! 127.03/127.30 Init Location: 0 127.03/127.30 Transitions: 127.03/127.30 <l0, l8, true> 127.03/127.30 <l1, l2, ((0 + conditional^0) <= 1)> 127.03/127.30 <l1, l3, (2 <= (0 + conditional^0)), par{num^0 -> (1 + num^0)}> 127.03/127.30 <l4, l3, ((0 + conditional^0) <= 1), par{IoCreateDevice^0 -> 0, i^0 -> (1 + i^0), status^0 -> 1}> 127.03/127.30 <l4, l1, (2 <= (0 + conditional^0)) /\ (undef37 = undef37), par{IoCreateDevice^0 -> 0, Pdo^0 -> 0, conditional^0 -> undef37}> 127.03/127.30 <l2, l5, true, par{PPBunlockInits^0 -> 1, num^0 -> 0}> 127.03/127.30 <l6, l2, ((0 + DName^0) <= 0)> 127.03/127.30 <l6, l4, (1 <= (0 + DName^0)) /\ (undef67 = undef67), par{IoCreateDevice^0 -> 1, conditional^0 -> undef67}> 127.03/127.30 <l3, l2, ((0 + Pdolen^0) <= (0 + i^0)), par{status^0 -> 0}> 127.03/127.30 <l3, l6, ((1 + i^0) <= (0 + Pdolen^0)) /\ (undef81 = undef81), par{DName^0 -> undef81, PPBlockInits^0 -> 1, status^0 -> 0}> 127.03/127.30 <l7, l3, (undef98 = undef98) /\ (undef96 = undef96), par{IoCreateDevice^0 -> 0, PPBlockInits^0 -> 1, PPBunlockInits^0 -> 0, Pdolen^0 -> undef96, i^0 -> undef98, status^0 -> 0}> 127.03/127.30 <l8, l7, true> 127.03/127.30 127.03/127.30 Fresh variables: 127.03/127.30 undef37, undef67, undef81, undef96, undef98, 127.03/127.31 127.03/127.31 Undef variables: 127.03/127.31 undef37, undef67, undef81, undef96, undef98, 127.03/127.31 127.03/127.31 Abstraction variables: 127.03/127.31 127.03/127.31 Exit nodes: 127.03/127.31 127.03/127.31 Accepting locations: 127.03/127.31 127.03/127.31 Asserts: 127.03/127.31 127.03/127.31 Preprocessed LLVMGraph 127.03/127.31 Init Location: 0 127.03/127.31 Transitions: 127.03/127.31 <l0, l3, (Pdolen^0 = undef96) /\ (i^0 = undef98) /\ (undef98 = undef98) /\ (undef96 = undef96)> 127.03/127.31 <l3, l5, ((0 + Pdolen^0) <= (0 + i^0)), par{num^0 -> 0}> 127.03/127.31 <l3, l5, ((1 + i^0) <= (0 + Pdolen^0)) /\ (undef81 = undef81) /\ ((0 + undef81) <= 0), par{num^0 -> 0}> 127.03/127.31 <l3, l3, ((1 + i^0) <= (0 + Pdolen^0)) /\ (undef81 = undef81) /\ (1 <= (0 + undef81)) /\ (undef67 = undef67) /\ ((0 + undef67) <= 1), par{i^0 -> (1 + i^0)}> 127.03/127.31 <l3, l5, ((1 + i^0) <= (0 + Pdolen^0)) /\ (undef81 = undef81) /\ (1 <= (0 + undef81)) /\ (undef67 = undef67) /\ (2 <= (0 + undef67)) /\ (undef37 = undef37) /\ ((0 + undef37) <= 1), par{num^0 -> 0}> 127.03/127.31 <l3, l3, ((1 + i^0) <= (0 + Pdolen^0)) /\ (undef81 = undef81) /\ (1 <= (0 + undef81)) /\ (undef67 = undef67) /\ (2 <= (0 + undef67)) /\ (undef37 = undef37) /\ (2 <= (0 + undef37)), par{num^0 -> (1 + num^0)}> 127.03/127.31 127.03/127.31 Fresh variables: 127.03/127.31 undef37, undef67, undef81, undef96, undef98, 127.03/127.31 127.03/127.31 Undef variables: 127.03/127.31 undef37, undef67, undef81, undef96, undef98, 127.03/127.31 127.03/127.31 Abstraction variables: 127.03/127.31 127.03/127.31 Exit nodes: 127.03/127.31 127.03/127.31 Accepting locations: 127.03/127.31 127.03/127.31 Asserts: 127.03/127.31 127.03/127.31 ************************************************************* 127.03/127.31 ******************************************************************************************* 127.03/127.31 *********************** WORKING TRANSITION SYSTEM (DAG) *********************** 127.03/127.31 ******************************************************************************************* 127.03/127.31 127.03/127.31 Init Location: 0 127.03/127.31 Graph 0: 127.03/127.31 Transitions: 127.03/127.31 Variables: 127.03/127.31 127.03/127.31 Graph 1: 127.03/127.31 Transitions: 127.03/127.31 <l3, l3, 1 + i^0 <= Pdolen^0 /\ 1 <= undef81 /\ undef67 <= 1, {i^0 -> 1 + i^0, rest remain the same}> 127.03/127.31 <l3, l3, 1 + i^0 <= Pdolen^0 /\ 1 <= undef81 /\ 2 <= undef37 /\ 2 <= undef67, {num^0 -> 1 + num^0, rest remain the same}> 127.03/127.31 Variables: 127.03/127.31 Pdolen^0, i^0, num^0 127.03/127.31 127.03/127.31 Graph 2: 127.03/127.31 Transitions: 127.03/127.31 Variables: 127.03/127.31 127.03/127.31 Precedence: 127.03/127.31 Graph 0 127.03/127.31 127.03/127.31 Graph 1 127.03/127.31 <l0, l3, Pdolen^0 = undef96 /\ i^0 = undef98, {all remain the same}> 127.03/127.31 127.03/127.31 Graph 2 127.03/127.31 <l3, l5, Pdolen^0 <= i^0, {num^0 -> 0, rest remain the same}> 127.03/127.31 <l3, l5, undef81 <= 0 /\ 1 + i^0 <= Pdolen^0, {num^0 -> 0, rest remain the same}> 127.03/127.31 <l3, l5, 1 + i^0 <= Pdolen^0 /\ 1 <= undef81 /\ 2 <= undef67 /\ undef37 <= 1, {num^0 -> 0, rest remain the same}> 127.03/127.31 127.03/127.31 Map Locations to Subgraph: 127.03/127.31 ( 0 , 0 ) 127.03/127.31 ( 3 , 1 ) 127.03/127.31 ( 5 , 2 ) 127.03/127.31 127.03/127.31 ******************************************************************************************* 127.03/127.31 ******************************** CHECKING ASSERTIONS ******************************** 127.03/127.31 ******************************************************************************************* 127.03/127.31 127.03/127.31 Proving termination of subgraph 0
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