details

property	value
status	complete
benchmark	06.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n057.star.cs.uiowa.edu
space	Gebhardt_06

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	281.306 seconds
cpu usage	1102.96
user time	1087.59
system time	15.371
max virtual memory	8.465284E7
max residence set size	1.3866128E7

stage attributes

key	value
starexec-result	NO

output

1101.98/281.10 NO 1102.78/281.23 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 1102.78/281.23 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 1102.78/281.23 1102.78/281.23 1102.78/281.23 Termination w.r.t. Q of the given QTRS could be disproven: 1102.78/281.23 1102.78/281.23 (0) QTRS 1102.78/281.23 (1) NonTerminationProof [COMPLETE, 33.0 s] 1102.78/281.23 (2) NO 1102.78/281.23 1102.78/281.23 1102.78/281.23 ---------------------------------------- 1102.78/281.23 1102.78/281.23 (0) 1102.78/281.23 Obligation: 1102.78/281.23 Q restricted rewrite system: 1102.78/281.23 The TRS R consists of the following rules: 1102.78/281.23 1102.78/281.23 0(0(0(0(x1)))) -> 0(1(0(1(x1)))) 1102.78/281.23 1(0(0(1(x1)))) -> 0(1(0(0(x1)))) 1102.78/281.23 1102.78/281.23 Q is empty. 1102.78/281.23 1102.78/281.23 ---------------------------------------- 1102.78/281.23 1102.78/281.23 (1) NonTerminationProof (COMPLETE) 1102.78/281.23 We used the non-termination processor [OPPELT08] to show that the SRS problem is infinite. 1102.78/281.23 1102.78/281.23 Found the self-embedding DerivationStructure: 1102.78/281.23 "0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 -> 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1" 1102.78/281.23 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 -> 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 -> 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 -> 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 -> 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 -> 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 0 0 1 0 1 0 1 1 0 0 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 0 0 1 0 0 0 1 0 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 1 0 1 0 0 1 0 0 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 1 0 0 1 0 0 0 0 1 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 1 0 1 0 0 1 0 0 1 0 1 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 0 0 0 0 1 0 -> 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 0 0 1 -> 0 0 1 0 0 0 0 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 -> 0 1 0 0 1 0 0 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 0 0 1 0 -> 0 0 0 1 0 0 0 1 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 0 -> 0 0 1 0 0 1 0 1 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 0 0 1 -> 0 0 1 0 0 0 0 1102.78/281.23 by OverlapClosure OC 3"0 0 0 0 0 0 1 -> 0 1 0 0 1 0 0 1102.78/281.23 by OverlapClosure OC 2"0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)""""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""1 0 0 1 -> 0 1 0 0 1102.78/281.23 by original rule (OC 1)"""0 0 0 0 -> 0 1 0 1 1102.78/281.23 by original rule (OC 1)" 1102.78/281.23 1102.78/281.23 ---------------------------------------- 1102.78/281.23 1102.78/281.23 (2) 1102.78/281.23 NO 1102.87/281.30 EOF popout

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actions

all output return to SRS_Standard 2019-03-29 03.29