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SRS_Standard 2019-03-29 03.29 pair #432289424
details
property
value
status
complete
benchmark
11.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n111.star.cs.uiowa.edu
space
Bouchare_06
run statistics
property
value
solver
matchbox-2019-03-17
configuration
std.sh
runtime (wallclock)
32.0209 seconds
cpu usage
126.495
user time
106.584
system time
19.9108
max virtual memory
1.16954772E8
max residence set size
1217416.0
stage attributes
key
value
starexec-result
YES
output
123.23/31.10 YES 123.23/31.10 property Termination 123.23/31.10 has value True 123.23/31.10 for SRS ( [a, a, a] -> [b], [b, b] -> [a, a], [a, a] -> [a, b, a]) 123.23/31.10 reason 123.23/31.10 remap for 3 rules 123.23/31.10 property Termination 123.23/31.10 has value True 123.23/31.10 for SRS ( [0, 0, 0] -> [1], [1, 1] -> [0, 0], [0, 0] -> [0, 1, 0]) 123.23/31.10 reason 123.23/31.10 DP transform 123.23/31.10 property Termination 123.23/31.10 has value True 123.23/31.10 for SRS ( [0, 0, 0] ->= [1], [1, 1] ->= [0, 0], [0, 0] ->= [0, 1, 0], [0#, 0, 0] |-> [1#], [1#, 1] |-> [0#, 0], [1#, 1] |-> [0#], [0#, 0] |-> [0#, 1, 0], [0#, 0] |-> [1#, 0]) 123.23/31.11 reason 123.23/31.11 remap for 8 rules 123.23/31.11 property Termination 123.23/31.11 has value True 123.23/31.11 for SRS ( [0, 0, 0] ->= [1], [1, 1] ->= [0, 0], [0, 0] ->= [0, 1, 0], [2, 0, 0] |-> [3], [3, 1] |-> [2, 0], [3, 1] |-> [2], [2, 0] |-> [2, 1, 0], [2, 0] |-> [3, 0]) 123.23/31.11 reason 123.23/31.11 EDG has 1 SCCs 123.23/31.11 property Termination 123.23/31.11 has value True 123.23/31.11 for SRS ( [2, 0, 0] |-> [3], [3, 1] |-> [2], [2, 0] |-> [3, 0], [3, 1] |-> [2, 0], [2, 0] |-> [2, 1, 0], [0, 0, 0] ->= [1], [1, 1] ->= [0, 0], [0, 0] ->= [0, 1, 0]) 123.23/31.11 reason 123.23/31.11 Matrix { monotone = Weak, domain = Arctic, bits = 3, dim = 4, solver = Minisatapi, verbose = False, tracing = False} 123.23/31.11 interpretation 123.23/31.11 0 Wk / 2A 4A 2A 3A \ 123.23/31.11 | 0A 2A - 1A | 123.23/31.11 | - 0A - - | 123.23/31.11 \ - - - 0A / 123.23/31.11 1 Wk / 0A - 4A 0A \ 123.23/31.11 | - - 2A - | 123.23/31.11 | 0A 2A 2A 1A | 123.23/31.11 \ - - - 0A / 123.23/31.11 2 Wk / 0A 0A 0A 2A \ 123.23/31.11 | - - - - | 123.23/31.11 | - 0A - 2A | 123.23/31.11 \ - - - 0A / 123.23/31.11 3 Wk / - 1A 2A 2A \ 123.23/31.11 | - - - - | 123.23/31.11 | - 0A 2A 1A | 123.23/31.11 \ - - - 0A / 123.23/31.11 [2, 0, 0] |-> [3] 123.23/31.13 lhs rhs ge gt 123.23/31.13 Wk / 4A 6A 4A 5A \ Wk / - 1A 2A 2A \ True False 123.23/31.13 | - - - - | | - - - - | 123.23/31.13 | 2A 4A 2A 3A | | - 0A 2A 1A | 123.23/31.13 \ - - - 0A / \ - - - 0A / 123.23/31.13 [3, 1] |-> [2] 123.23/31.16 lhs rhs ge gt 123.23/31.16 Wk / 2A 4A 4A 3A \ Wk / 0A 0A 0A 2A \ True True 123.23/31.16 | - - - - | | - - - - | 123.23/31.16 | 2A 4A 4A 3A | | - 0A - 2A | 123.23/31.16 \ - - - 0A / \ - - - 0A / 123.23/31.16 [2, 0] |-> [3, 0] 123.23/31.17 lhs rhs ge gt 123.23/31.17 Wk / 2A 4A 2A 3A \ Wk / 1A 3A - 2A \ True False 123.23/31.17 | - - - - | | - - - - | 123.23/31.17 | 0A 2A - 2A | | 0A 2A - 1A | 123.23/31.17 \ - - - 0A / \ - - - 0A / 123.23/31.17 [3, 1] |-> [2, 0] 123.61/31.21 lhs rhs ge gt 123.61/31.21 Wk / 2A 4A 4A 3A \ Wk / 2A 4A 2A 3A \ True False 123.61/31.21 | - - - - | | - - - - | 123.61/31.21 | 2A 4A 4A 3A | | 0A 2A - 2A | 123.61/31.21 \ - - - 0A / \ - - - 0A / 123.61/31.21 [2, 0] |-> [2, 1, 0] 123.61/31.24 lhs rhs ge gt 123.61/31.25 Wk / 2A 4A 2A 3A \ Wk / 2A 4A 2A 3A \ True False 123.61/31.25 | - - - - | | - - - - | 123.61/31.25 | 0A 2A - 2A | | - 2A - 2A | 123.61/31.25 \ - - - 0A / \ - - - 0A / 123.61/31.25 [0, 0, 0] ->= [1] 123.61/31.29 lhs rhs ge gt 123.61/31.29 Wk / 6A 8A 6A 7A \ Wk / 0A - 4A 0A \ True False 123.61/31.29 | 4A 6A 4A 5A | | - - 2A - | 123.61/31.29 | 2A 4A 2A 3A | | 0A 2A 2A 1A | 123.61/31.29 \ - - - 0A / \ - - - 0A / 123.61/31.29 [1, 1] ->= [0, 0] 123.61/31.29 lhs rhs ge gt 123.61/31.29 Wk / 4A 6A 6A 5A \ Wk / 4A 6A 4A 5A \ True False 123.61/31.30 | 2A 4A 4A 3A | | 2A 4A 2A 3A | 123.61/31.30 | 2A 4A 4A 3A | | 0A 2A - 1A | 123.61/31.30 \ - - - 0A / \ - - - 0A / 123.61/31.30 [0, 0] ->= [0, 1, 0] 123.61/31.30 lhs rhs ge gt 123.91/31.30 Wk / 4A 6A 4A 5A \ Wk / 4A 6A 4A 5A \ True False 123.91/31.30 | 2A 4A 2A 3A | | 2A 4A 2A 3A | 123.91/31.30 | 0A 2A - 1A | | - 2A - - | 123.91/31.30 \ - - - 0A / \ - - - 0A / 123.91/31.30 property Termination 123.91/31.30 has value True 123.91/31.30 for SRS ( [2, 0, 0] |-> [3], [2, 0] |-> [3, 0], [3, 1] |-> [2, 0], [2, 0] |-> [2, 1, 0], [0, 0, 0] ->= [1], [1, 1] ->= [0, 0], [0, 0] ->= [0, 1, 0]) 123.91/31.30 reason 123.91/31.30 EDG has 1 SCCs 123.91/31.31 property Termination 123.91/31.31 has value True 123.91/31.32 for SRS ( [2, 0, 0] |-> [3], [3, 1] |-> [2, 0], [2, 0] |-> [2, 1, 0], [2, 0] |-> [3, 0], [0, 0, 0] ->= [1], [1, 1] ->= [0, 0], [0, 0] ->= [0, 1, 0]) 123.91/31.32 reason
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