details

property	value
status	complete
benchmark	size-12-alpha-3-num-170.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n097.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	13.6936 seconds
cpu usage	48.2945
user time	46.4283
system time	1.86623
max virtual memory	6.0219108E7
max residence set size	4595676.0

stage attributes

key	value
starexec-result	NO

output

48.12/13.61 NO 48.12/13.62 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 48.12/13.62 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 48.12/13.62 48.12/13.62 48.12/13.62 Termination w.r.t. Q of the given QTRS could be disproven: 48.12/13.62 48.12/13.62 (0) QTRS 48.12/13.62 (1) NonTerminationProof [COMPLETE, 2173 ms] 48.12/13.62 (2) NO 48.12/13.62 48.12/13.62 48.12/13.62 ---------------------------------------- 48.12/13.62 48.12/13.62 (0) 48.12/13.62 Obligation: 48.12/13.62 Q restricted rewrite system: 48.12/13.62 The TRS R consists of the following rules: 48.12/13.62 48.12/13.62 a(x1) -> x1 48.12/13.62 a(b(x1)) -> b(a(c(a(x1)))) 48.12/13.62 c(b(x1)) -> x1 48.12/13.62 c(c(x1)) -> b(x1) 48.12/13.62 48.12/13.62 Q is empty. 48.12/13.62 48.12/13.62 ---------------------------------------- 48.12/13.62 48.12/13.62 (1) NonTerminationProof (COMPLETE) 48.12/13.62 We used the non-termination processor [OPPELT08] to show that the SRS problem is infinite. 48.12/13.62 48.12/13.62 Found the self-embedding DerivationStructure: 48.12/13.62 "a b b c b b c -> b b a b b c b b c" 48.12/13.62 a b b c b b c -> b b a b b c b b c 48.12/13.62 by OverlapClosure OC 3"a b b c b b c -> b b a b b a c b b c 48.12/13.62 by OverlapClosure OC 2"a b b c -> b b a b a 48.12/13.62 by OverlapClosure OC 3"a b b c -> b b a c c a 48.12/13.62 by OverlapClosure OC 3"a b b c -> b a b c a 48.12/13.62 by OverlapClosure OC 2"a b b c -> b a a b 48.12/13.62 by OverlapClosure OC 3"a b b c -> b a c b a b 48.12/13.62 by OverlapClosure OC 2"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a b c -> b a b 48.12/13.62 by OverlapClosure OC 2"a b -> b a c 48.12/13.62 by OverlapClosure OC 2"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a -> 48.12/13.62 by original rule (OC 1)"""c c -> b 48.12/13.62 by original rule (OC 1)""""c b -> 48.12/13.62 by original rule (OC 1)"""a b -> b c a 48.12/13.62 by OverlapClosure OC 3"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a -> 48.12/13.62 by original rule (OC 1)""""a b -> b a c 48.12/13.62 by OverlapClosure OC 2"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a -> 48.12/13.62 by original rule (OC 1)""""c c -> b 48.12/13.62 by original rule (OC 1)"""a b b c -> b a c b b c 48.12/13.62 by OverlapClosure OC 3"a b b c -> b a c b b a c 48.12/13.62 by OverlapClosure OC 2"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a b c -> b b a c 48.12/13.62 by OverlapClosure OC 2"a b c -> b a b 48.12/13.62 by OverlapClosure OC 2"a b -> b a c 48.12/13.62 by OverlapClosure OC 2"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a -> 48.12/13.62 by original rule (OC 1)"""c c -> b 48.12/13.62 by original rule (OC 1)"""a b -> b a c 48.12/13.62 by OverlapClosure OC 2"a b -> b a c a 48.12/13.62 by original rule (OC 1)""a -> 48.12/13.62 by original rule (OC 1)"""""a -> 48.12/13.62 by original rule (OC 1)""""a -> 48.12/13.62 by original rule (OC 1)" 48.12/13.62 48.12/13.62 ---------------------------------------- 48.12/13.62 48.12/13.62 (2) 48.12/13.62 NO 48.24/13.69 EOF popout

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job log

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actions

all output return to SRS_Standard 2019-03-29 03.29