details

property	value
status	complete
benchmark	size-12-alpha-3-num-104.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n164.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	matchbox-2019-03-17
configuration	std.sh
runtime (wallclock)	6.57214 seconds
cpu usage	25.7723
user time	22.3753
system time	3.39704
max virtual memory	1.16749704E8
max residence set size	638616.0

stage attributes

key	value
starexec-result	YES

output

25.31/6.48 YES 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [a] -> [], [a, a, b] -> [b, a, b, a], [b, b] -> [c, a]) 25.31/6.48 reason 25.31/6.48 remap for 3 rules 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [0] -> [], [0, 0, 1] -> [1, 0, 1, 0], [1, 1] -> [2, 0]) 25.31/6.48 reason 25.31/6.48 reverse each lhs and rhs 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [0] -> [], [1, 0, 0] -> [0, 1, 0, 1], [1, 1] -> [0, 2]) 25.31/6.48 reason 25.31/6.48 DP transform 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [0] ->= [], [1, 0, 0] ->= [0, 1, 0, 1], [1, 1] ->= [0, 2], [1#, 0, 0] |-> [0#, 1, 0, 1], [1#, 0, 0] |-> [1#, 0, 1], [1#, 0, 0] |-> [0#, 1], [1#, 0, 0] |-> [1#], [1#, 1] |-> [0#, 2]) 25.31/6.48 reason 25.31/6.48 remap for 8 rules 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [0] ->= [], [1, 0, 0] ->= [0, 1, 0, 1], [1, 1] ->= [0, 2], [3, 0, 0] |-> [4, 1, 0, 1], [3, 0, 0] |-> [3, 0, 1], [3, 0, 0] |-> [4, 1], [3, 0, 0] |-> [3], [3, 1] |-> [4, 2]) 25.31/6.48 reason 25.31/6.48 weights 25.31/6.48 Map [(3, 3/1)] 25.31/6.48 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [0] ->= [], [1, 0, 0] ->= [0, 1, 0, 1], [1, 1] ->= [0, 2], [3, 0, 0] |-> [3, 0, 1], [3, 0, 0] |-> [3]) 25.31/6.48 reason 25.31/6.48 EDG has 1 SCCs 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [3, 0, 0] |-> [3, 0, 1], [3, 0, 0] |-> [3], [0] ->= [], [1, 0, 0] ->= [0, 1, 0, 1], [1, 1] ->= [0, 2]) 25.31/6.48 reason 25.31/6.48 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 5, solver = Minisatapi, verbose = False, tracing = True} 25.31/6.48 interpretation 25.31/6.48 0 / 0A 0A 0A 5A 5A \ 25.31/6.48 | 0A 0A 0A 5A 5A | 25.31/6.48 | 0A 0A 0A 0A 5A | 25.31/6.48 | -5A 0A 0A 0A 0A | 25.31/6.48 \ -5A -5A 0A 0A 0A / 25.31/6.48 1 / 0A 0A 0A 0A 5A \ 25.31/6.48 | 0A 0A 0A 0A 0A | 25.31/6.48 | -5A 0A 0A 0A 0A | 25.31/6.48 | -5A -5A -5A -5A 0A | 25.31/6.48 \ -5A -5A -5A -5A 0A / 25.31/6.48 2 / 0A 0A 0A 0A 0A \ 25.31/6.48 | -5A -5A -5A -5A 0A | 25.31/6.48 | -5A -5A -5A -5A 0A | 25.31/6.48 | -5A -5A -5A -5A 0A | 25.31/6.48 \ -5A -5A -5A -5A -5A / 25.31/6.48 3 / 16A 16A 20A 21A 21A \ 25.31/6.48 | 16A 16A 20A 21A 21A | 25.31/6.48 | 16A 16A 20A 21A 21A | 25.31/6.48 | 16A 16A 20A 21A 21A | 25.31/6.48 \ 16A 16A 20A 21A 21A / 25.31/6.48 [3, 0, 0] |-> [3, 0, 1] 25.31/6.48 lhs rhs ge gt 25.31/6.48 / 21A 21A 25A 26A 26A \ / 21A 21A 21A 21A 25A \ True False 25.31/6.48 | 21A 21A 25A 26A 26A | | 21A 21A 21A 21A 25A | 25.31/6.48 | 21A 21A 25A 26A 26A | | 21A 21A 21A 21A 25A | 25.31/6.48 | 21A 21A 25A 26A 26A | | 21A 21A 21A 21A 25A | 25.31/6.48 \ 21A 21A 25A 26A 26A / \ 21A 21A 21A 21A 25A / 25.31/6.48 [3, 0, 0] |-> [3] 25.31/6.48 lhs rhs ge gt 25.31/6.48 / 21A 21A 25A 26A 26A \ / 16A 16A 20A 21A 21A \ True True 25.31/6.48 | 21A 21A 25A 26A 26A | | 16A 16A 20A 21A 21A | 25.31/6.48 | 21A 21A 25A 26A 26A | | 16A 16A 20A 21A 21A | 25.31/6.48 | 21A 21A 25A 26A 26A | | 16A 16A 20A 21A 21A | 25.31/6.48 \ 21A 21A 25A 26A 26A / \ 16A 16A 20A 21A 21A / 25.31/6.48 [0] ->= [] 25.31/6.48 lhs rhs ge gt 25.31/6.48 / 0A 0A 0A 5A 5A \ / 0A - - - - \ True False 25.31/6.48 | 0A 0A 0A 5A 5A | | - 0A - - - | 25.31/6.48 | 0A 0A 0A 0A 5A | | - - 0A - - | 25.31/6.48 | -5A 0A 0A 0A 0A | | - - - 0A - | 25.31/6.48 \ -5A -5A 0A 0A 0A / \ - - - - 0A / 25.31/6.48 [1, 0, 0] ->= [0, 1, 0, 1] 25.31/6.48 lhs rhs ge gt 25.31/6.48 / 5A 5A 5A 5A 10A \ / 0A 5A 5A 5A 5A \ True False 25.31/6.48 | 0A 5A 5A 5A 5A | | 0A 5A 5A 5A 5A | 25.31/6.48 | 0A 5A 5A 5A 5A | | 0A 5A 5A 5A 5A | 25.31/6.48 | 0A 0A 0A 0A 5A | | 0A 0A 0A 0A 5A | 25.31/6.48 \ 0A 0A 0A 0A 5A / \ 0A 0A 0A 0A 5A / 25.31/6.48 [1, 1] ->= [0, 2] 25.31/6.48 lhs rhs ge gt 25.31/6.48 / 0A 0A 0A 0A 5A \ / 0A 0A 0A 0A 5A \ True False 25.31/6.48 | 0A 0A 0A 0A 5A | | 0A 0A 0A 0A 5A | 25.31/6.48 | 0A 0A 0A 0A 0A | | 0A 0A 0A 0A 0A | 25.31/6.48 | -5A -5A -5A -5A 0A | | -5A -5A -5A -5A 0A | 25.31/6.48 \ -5A -5A -5A -5A 0A / \ -5A -5A -5A -5A 0A / 25.31/6.48 property Termination 25.31/6.48 has value True 25.31/6.48 for SRS ( [3, 0, 0] |-> [3, 0, 1], [0] ->= [], [1, 0, 0] ->= [0, 1, 0, 1], [1, 1] ->= [0, 2]) 25.31/6.48 reason 25.31/6.48 EDG has 1 SCCs 25.31/6.48 property Termination popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS_Standard 2019-03-29 03.29