details

property	value
status	complete
benchmark	size-12-alpha-2-num-22.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n105.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	matchbox-2019-03-17
configuration	std.sh
runtime (wallclock)	1.93947 seconds
cpu usage	7.4096
user time	6.39374
system time	1.01586
max virtual memory	1.16817292E8
max residence set size	229096.0

stage attributes

key	value
starexec-result	YES

output

4.04/1.06 YES 4.04/1.06 property Termination 4.04/1.06 has value True 4.04/1.06 for SRS ( [a] -> [], [a, a, b, a] -> [b, b, a, a, a], [b] -> [a]) 4.04/1.06 reason 4.04/1.06 remap for 3 rules 4.04/1.06 property Termination 4.04/1.06 has value True 4.04/1.06 for SRS ( [0] -> [], [0, 0, 1, 0] -> [1, 1, 0, 0, 0], [1] -> [0]) 4.04/1.06 reason 4.04/1.06 DP transform 4.04/1.06 property Termination 4.04/1.06 has value True 4.04/1.06 for SRS ( [0] ->= [], [0, 0, 1, 0] ->= [1, 1, 0, 0, 0], [1] ->= [0], [0#, 0, 1, 0] |-> [1#, 1, 0, 0, 0], [0#, 0, 1, 0] |-> [1#, 0, 0, 0], [0#, 0, 1, 0] |-> [0#, 0, 0], [0#, 0, 1, 0] |-> [0#, 0], [1#] |-> [0#]) 4.04/1.06 reason 4.04/1.06 remap for 8 rules 4.04/1.06 property Termination 4.04/1.06 has value True 4.04/1.06 for SRS ( [0] ->= [], [0, 0, 1, 0] ->= [1, 1, 0, 0, 0], [1] ->= [0], [2, 0, 1, 0] |-> [3, 1, 0, 0, 0], [2, 0, 1, 0] |-> [3, 0, 0, 0], [2, 0, 1, 0] |-> [2, 0, 0], [2, 0, 1, 0] |-> [2, 0], [3] |-> [2]) 4.04/1.06 reason 4.04/1.06 EDG has 1 SCCs 4.04/1.06 property Termination 4.04/1.06 has value True 4.04/1.06 for SRS ( [2, 0, 1, 0] |-> [3, 1, 0, 0, 0], [3] |-> [2], [2, 0, 1, 0] |-> [2, 0], [2, 0, 1, 0] |-> [2, 0, 0], [2, 0, 1, 0] |-> [3, 0, 0, 0], [0] ->= [], [0, 0, 1, 0] ->= [1, 1, 0, 0, 0], [1] ->= [0]) 4.04/1.06 reason 4.04/1.06 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = True} 4.04/1.06 interpretation 4.04/1.06 0 / 0A 2A \ 4.04/1.06 \ -2A 0A / 4.04/1.06 1 / 0A 2A \ 4.04/1.06 \ 0A 0A / 4.04/1.06 2 / 23A 25A \ 4.04/1.06 \ 23A 25A / 4.04/1.06 3 / 25A 25A \ 4.04/1.06 \ 25A 25A / 4.04/1.06 [2, 0, 1, 0] |-> [3, 1, 0, 0, 0] 4.04/1.06 lhs rhs ge gt 4.04/1.06 / 25A 27A \ / 25A 27A \ True False 4.04/1.06 \ 25A 27A / \ 25A 27A / 4.04/1.06 [3] |-> [2] 4.04/1.06 lhs rhs ge gt 4.04/1.06 / 25A 25A \ / 23A 25A \ True False 4.04/1.06 \ 25A 25A / \ 23A 25A / 4.04/1.06 [2, 0, 1, 0] |-> [2, 0] 4.04/1.06 lhs rhs ge gt 4.04/1.06 / 25A 27A \ / 23A 25A \ True True 4.04/1.06 \ 25A 27A / \ 23A 25A / 4.04/1.06 [2, 0, 1, 0] |-> [2, 0, 0] 4.04/1.06 lhs rhs ge gt 4.04/1.06 / 25A 27A \ / 23A 25A \ True True 4.04/1.06 \ 25A 27A / \ 23A 25A / 4.04/1.06 [2, 0, 1, 0] |-> [3, 0, 0, 0] 4.04/1.06 lhs rhs ge gt 4.04/1.06 / 25A 27A \ / 25A 27A \ True False 4.04/1.06 \ 25A 27A / \ 25A 27A / 4.04/1.07 [0] ->= [] 4.04/1.07 lhs rhs ge gt 4.04/1.07 / 0A 2A \ / 0A - \ True False 4.04/1.07 \ -2A 0A / \ - 0A / 4.04/1.07 [0, 0, 1, 0] ->= [1, 1, 0, 0, 0] 4.04/1.07 lhs rhs ge gt 4.04/1.07 / 2A 4A \ / 2A 4A \ True False 4.04/1.07 \ 0A 2A / \ 0A 2A / 4.04/1.07 [1] ->= [0] 4.04/1.07 lhs rhs ge gt 4.04/1.07 / 0A 2A \ / 0A 2A \ True False 4.04/1.07 \ 0A 0A / \ -2A 0A / 4.04/1.07 property Termination 4.04/1.07 has value True 4.24/1.09 for SRS ( [2, 0, 1, 0] |-> [3, 1, 0, 0, 0], [3] |-> [2], [2, 0, 1, 0] |-> [3, 0, 0, 0], [0] ->= [], [0, 0, 1, 0] ->= [1, 1, 0, 0, 0], [1] ->= [0]) 4.24/1.09 reason 4.24/1.09 EDG has 1 SCCs 4.24/1.09 property Termination 4.24/1.09 has value True 4.24/1.09 for SRS ( [2, 0, 1, 0] |-> [3, 1, 0, 0, 0], [3] |-> [2], [2, 0, 1, 0] |-> [3, 0, 0, 0], [0] ->= [], [0, 0, 1, 0] ->= [1, 1, 0, 0, 0], [1] ->= [0]) 4.24/1.09 reason 4.24/1.09 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = True} 4.24/1.09 interpretation 4.24/1.09 0 / 0A 0A \ 4.24/1.09 \ 0A 0A / 4.24/1.09 1 / 0A 2A \ 4.24/1.09 \ 0A 0A / 4.24/1.09 2 / 10A 12A \ 4.24/1.09 \ 10A 12A / 4.24/1.09 3 / 10A 12A \ 4.24/1.09 \ 10A 12A / 4.24/1.09 [2, 0, 1, 0] |-> [3, 1, 0, 0, 0] 4.24/1.09 lhs rhs ge gt 4.24/1.09 / 14A 14A \ / 12A 12A \ True True 4.24/1.09 \ 14A 14A / \ 12A 12A / 4.24/1.09 [3] |-> [2] 4.24/1.09 lhs rhs ge gt 4.24/1.09 / 10A 12A \ / 10A 12A \ True False 4.24/1.09 \ 10A 12A / \ 10A 12A / 4.24/1.09 [2, 0, 1, 0] |-> [3, 0, 0, 0] 4.24/1.09 lhs rhs ge gt 4.24/1.09 / 14A 14A \ / 12A 12A \ True True 4.24/1.09 \ 14A 14A / \ 12A 12A / 4.24/1.09 [0] ->= [] 4.24/1.09 lhs rhs ge gt popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS_Standard 2019-03-29 03.29