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SRS_Standard 2019-03-29 03.29 pair #432290114
details
property
value
status
complete
benchmark
size-12-alpha-3-num-124.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n089.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
matchbox-2019-03-17
configuration
std.sh
runtime (wallclock)
10.4917 seconds
cpu usage
41.0756
user time
35.2386
system time
5.83706
max virtual memory
1.16682116E8
max residence set size
1468284.0
stage attributes
key
value
starexec-result
YES
output
40.22/10.23 YES 40.39/10.24 property Termination 40.46/10.25 has value True 40.46/10.25 for SRS ( [a] -> [], [a, a, b] -> [c, b, b, a, a], [b, c] -> [a]) 40.46/10.25 reason 40.46/10.26 remap for 3 rules 40.46/10.26 property Termination 40.46/10.26 has value True 40.46/10.26 for SRS ( [0] -> [], [0, 0, 1] -> [2, 1, 1, 0, 0], [1, 2] -> [0]) 40.46/10.26 reason 40.46/10.26 DP transform 40.46/10.26 property Termination 40.46/10.26 has value True 40.46/10.26 for SRS ( [0] ->= [], [0, 0, 1] ->= [2, 1, 1, 0, 0], [1, 2] ->= [0], [0#, 0, 1] |-> [1#, 1, 0, 0], [0#, 0, 1] |-> [1#, 0, 0], [0#, 0, 1] |-> [0#, 0], [0#, 0, 1] |-> [0#], [1#, 2] |-> [0#]) 40.46/10.26 reason 40.46/10.26 remap for 8 rules 40.46/10.26 property Termination 40.46/10.26 has value True 40.46/10.26 for SRS ( [0] ->= [], [0, 0, 1] ->= [2, 1, 1, 0, 0], [1, 2] ->= [0], [3, 0, 1] |-> [4, 1, 0, 0], [3, 0, 1] |-> [4, 0, 0], [3, 0, 1] |-> [3, 0], [3, 0, 1] |-> [3], [4, 2] |-> [3]) 40.46/10.26 reason 40.46/10.26 EDG has 1 SCCs 40.46/10.26 property Termination 40.46/10.26 has value True 40.46/10.27 for SRS ( [3, 0, 1] |-> [4, 1, 0, 0], [4, 2] |-> [3], [3, 0, 1] |-> [3], [3, 0, 1] |-> [3, 0], [3, 0, 1] |-> [4, 0, 0], [0] ->= [], [0, 0, 1] ->= [2, 1, 1, 0, 0], [1, 2] ->= [0]) 40.46/10.27 reason 40.46/10.27 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = True} 40.46/10.27 interpretation 40.46/10.27 0 / 0A 0A 3A \ 40.46/10.27 | 0A 0A 0A | 40.46/10.27 \ -3A -3A 0A / 40.46/10.27 1 / 0A 3A 3A \ 40.46/10.27 | 0A 0A 3A | 40.46/10.27 \ 0A 0A 3A / 40.46/10.27 2 / 0A 0A 0A \ 40.46/10.27 | -3A 0A 0A | 40.46/10.27 \ -3A -3A -3A / 40.46/10.27 3 / 38A 41A 41A \ 40.46/10.27 | 38A 41A 41A | 40.46/10.27 \ 38A 41A 41A / 40.46/10.27 4 / 38A 41A 41A \ 40.46/10.27 | 38A 41A 41A | 40.46/10.27 \ 38A 41A 41A / 40.46/10.27 [3, 0, 1] |-> [4, 1, 0, 0] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 41A 44A 44A \ / 41A 41A 44A \ True False 40.46/10.27 | 41A 44A 44A | | 41A 41A 44A | 40.46/10.27 \ 41A 44A 44A / \ 41A 41A 44A / 40.46/10.27 [4, 2] |-> [3] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 38A 41A 41A \ / 38A 41A 41A \ True False 40.46/10.27 | 38A 41A 41A | | 38A 41A 41A | 40.46/10.27 \ 38A 41A 41A / \ 38A 41A 41A / 40.46/10.27 [3, 0, 1] |-> [3] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 41A 44A 44A \ / 38A 41A 41A \ True True 40.46/10.27 | 41A 44A 44A | | 38A 41A 41A | 40.46/10.27 \ 41A 44A 44A / \ 38A 41A 41A / 40.46/10.27 [3, 0, 1] |-> [3, 0] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 41A 44A 44A \ / 41A 41A 41A \ True False 40.46/10.27 | 41A 44A 44A | | 41A 41A 41A | 40.46/10.27 \ 41A 44A 44A / \ 41A 41A 41A / 40.46/10.27 [3, 0, 1] |-> [4, 0, 0] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 41A 44A 44A \ / 41A 41A 44A \ True False 40.46/10.27 | 41A 44A 44A | | 41A 41A 44A | 40.46/10.27 \ 41A 44A 44A / \ 41A 41A 44A / 40.46/10.27 [0] ->= [] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 0A 0A 3A \ / 0A - - \ True False 40.46/10.27 | 0A 0A 0A | | - 0A - | 40.46/10.27 \ -3A -3A 0A / \ - - 0A / 40.46/10.27 [0, 0, 1] ->= [2, 1, 1, 0, 0] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 3A 3A 6A \ / 3A 3A 6A \ True False 40.46/10.27 | 3A 3A 6A | | 3A 3A 6A | 40.46/10.27 \ 0A 0A 3A / \ 0A 0A 3A / 40.46/10.27 [1, 2] ->= [0] 40.46/10.27 lhs rhs ge gt 40.46/10.27 / 0A 3A 3A \ / 0A 0A 3A \ True False 40.46/10.27 | 0A 0A 0A | | 0A 0A 0A | 40.46/10.27 \ 0A 0A 0A / \ -3A -3A 0A / 40.46/10.27 property Termination 40.46/10.27 has value True 40.46/10.28 for SRS ( [3, 0, 1] |-> [4, 1, 0, 0], [4, 2] |-> [3], [3, 0, 1] |-> [3, 0], [3, 0, 1] |-> [4, 0, 0], [0] ->= [], [0, 0, 1] ->= [2, 1, 1, 0, 0], [1, 2] ->= [0]) 40.46/10.28 reason 40.46/10.28 EDG has 1 SCCs 40.46/10.28 property Termination 40.46/10.28 has value True 40.46/10.28 for SRS ( [3, 0, 1] |-> [4, 1, 0, 0], [4, 2] |-> [3], [3, 0, 1] |-> [4, 0, 0], [3, 0, 1] |-> [3, 0], [0] ->= [], [0, 0, 1] ->= [2, 1, 1, 0, 0], [1, 2] ->= [0]) 40.46/10.28 reason 40.46/10.28 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = True} 40.46/10.28 interpretation 40.46/10.28 0 / 0A 0A 0A \ 40.46/10.28 | 0A 0A 0A | 40.46/10.28 \ -3A 0A 0A / 40.46/10.28 1 / 0A 0A 0A \ 40.46/10.28 | -3A -3A 0A | 40.46/10.28 \ -3A -3A -3A / 40.46/10.28 2 / 0A 3A 3A \
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