details

property	value
status	complete
benchmark	size-12-alpha-3-num-127.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n121.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	14.374 seconds
cpu usage	52.5918
user time	51.0993
system time	1.49257
max virtual memory	4.2001788E7
max residence set size	4207188.0

stage attributes

key	value
starexec-result	NO

output

52.10/14.26 NO 52.10/14.29 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 52.10/14.29 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 52.10/14.29 52.10/14.29 52.10/14.29 Termination w.r.t. Q of the given QTRS could be disproven: 52.10/14.29 52.10/14.29 (0) QTRS 52.10/14.29 (1) NonTerminationProof [COMPLETE, 2666 ms] 52.10/14.29 (2) NO 52.10/14.29 52.10/14.29 52.10/14.29 ---------------------------------------- 52.10/14.29 52.10/14.29 (0) 52.10/14.29 Obligation: 52.10/14.29 Q restricted rewrite system: 52.10/14.29 The TRS R consists of the following rules: 52.10/14.29 52.10/14.29 a(x1) -> x1 52.10/14.29 a(a(b(x1))) -> c(c(c(x1))) 52.10/14.29 c(x1) -> b(a(x1)) 52.10/14.29 c(b(x1)) -> x1 52.10/14.29 52.10/14.29 Q is empty. 52.10/14.29 52.10/14.29 ---------------------------------------- 52.10/14.29 52.10/14.29 (1) NonTerminationProof (COMPLETE) 52.10/14.29 We used the non-termination processor [OPPELT08] to show that the SRS problem is infinite. 52.10/14.29 52.10/14.29 Found the self-embedding DerivationStructure: 52.10/14.29 "a a b a b a b -> b b a a b a b a b" 52.10/14.29 a a b a b a b -> b b a a b a b a b 52.10/14.29 by OverlapClosure OC 3"a a b a b a b -> b b a a c b a b 52.10/14.29 by OverlapClosure OC 2"a a b a b -> b b a a a 52.10/14.29 by OverlapClosure OC 3"a a b a b -> c a b a 52.10/14.29 by OverlapClosure OC 2"a a b -> c a 52.10/14.29 by OverlapClosure OC 3"a a b -> c c b a 52.10/14.29 by OverlapClosure OC 2"a a b -> c c c 52.10/14.29 by original rule (OC 1)""c -> b a 52.10/14.29 by original rule (OC 1)"""c b -> 52.10/14.29 by original rule (OC 1)"""a a b -> a b a 52.10/14.29 by OverlapClosure OC 3"a a b -> c b a b a 52.10/14.29 by OverlapClosure OC 3"a a b -> c c b a 52.10/14.29 by OverlapClosure OC 2"a a b -> c c c 52.10/14.29 by original rule (OC 1)""c -> b a 52.10/14.29 by original rule (OC 1)"""c -> b a 52.10/14.29 by original rule (OC 1)"""c b -> 52.10/14.29 by original rule (OC 1)""""c a b -> b b a a 52.10/14.29 by OverlapClosure OC 3"c a b -> b b a c b a 52.10/14.29 by OverlapClosure OC 2"c -> b a 52.10/14.29 by original rule (OC 1)""a a b -> b a c b a 52.10/14.29 by OverlapClosure OC 3"a a b -> c c b a 52.10/14.29 by OverlapClosure OC 2"a a b -> c c c 52.10/14.29 by original rule (OC 1)""c -> b a 52.10/14.29 by original rule (OC 1)"""c -> b a 52.10/14.29 by original rule (OC 1)""""c b -> 52.10/14.29 by original rule (OC 1)""""a a b -> c b a b 52.10/14.29 by OverlapClosure OC 2"a a b -> c b a c 52.10/14.29 by OverlapClosure OC 3"a a b -> c c c 52.10/14.29 by original rule (OC 1)""c -> b a 52.10/14.29 by original rule (OC 1)"""c -> b 52.10/14.29 by OverlapClosure OC 2"c -> b a 52.10/14.29 by original rule (OC 1)""a -> 52.10/14.29 by original rule (OC 1)"""""c -> b a 52.10/14.29 by original rule (OC 1)" 52.10/14.29 52.10/14.29 ---------------------------------------- 52.10/14.29 52.10/14.29 (2) 52.10/14.29 NO 52.50/14.37 EOF popout

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actions

all output return to SRS_Standard 2019-03-29 03.29