details

property	value
status	complete
benchmark	size-12-alpha-3-num-94.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n033.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	ttt2-1.19
configuration	ttt2
runtime (wallclock)	10.9146 seconds
cpu usage	41.3671
user time	40.3227
system time	1.04435
max virtual memory	3455984.0
max residence set size	83832.0

stage attributes

key	value
starexec-result	YES

output

41.08/10.72 YES 41.16/10.72 41.16/10.72 Problem: 41.16/10.72 a(x1) -> x1 41.16/10.72 a(a(x1)) -> b(c(x1)) 41.16/10.72 b(x1) -> x1 41.16/10.72 c(x1) -> x1 41.16/10.72 c(b(x1)) -> a(b(c(x1))) 41.16/10.72 41.16/10.72 Proof: 41.16/10.72 DP Processor: 41.16/10.72 DPs: 41.16/10.72 a#(a(x1)) -> c#(x1) 41.16/10.72 a#(a(x1)) -> b#(c(x1)) 41.16/10.72 c#(b(x1)) -> c#(x1) 41.16/10.72 c#(b(x1)) -> b#(c(x1)) 41.16/10.72 c#(b(x1)) -> a#(b(c(x1))) 41.16/10.72 TRS: 41.16/10.72 a(x1) -> x1 41.16/10.72 a(a(x1)) -> b(c(x1)) 41.16/10.72 b(x1) -> x1 41.16/10.72 c(x1) -> x1 41.16/10.72 c(b(x1)) -> a(b(c(x1))) 41.16/10.72 TDG Processor: 41.16/10.72 DPs: 41.16/10.72 a#(a(x1)) -> c#(x1) 41.16/10.72 a#(a(x1)) -> b#(c(x1)) 41.16/10.72 c#(b(x1)) -> c#(x1) 41.16/10.72 c#(b(x1)) -> b#(c(x1)) 41.16/10.72 c#(b(x1)) -> a#(b(c(x1))) 41.16/10.72 TRS: 41.16/10.72 a(x1) -> x1 41.16/10.72 a(a(x1)) -> b(c(x1)) 41.16/10.72 b(x1) -> x1 41.16/10.72 c(x1) -> x1 41.16/10.72 c(b(x1)) -> a(b(c(x1))) 41.16/10.72 graph: 41.16/10.72 c#(b(x1)) -> c#(x1) -> c#(b(x1)) -> a#(b(c(x1))) 41.16/10.72 c#(b(x1)) -> c#(x1) -> c#(b(x1)) -> b#(c(x1)) 41.16/10.72 c#(b(x1)) -> c#(x1) -> c#(b(x1)) -> c#(x1) 41.16/10.72 c#(b(x1)) -> a#(b(c(x1))) -> a#(a(x1)) -> b#(c(x1)) 41.16/10.72 c#(b(x1)) -> a#(b(c(x1))) -> a#(a(x1)) -> c#(x1) 41.16/10.72 a#(a(x1)) -> c#(x1) -> c#(b(x1)) -> a#(b(c(x1))) 41.16/10.72 a#(a(x1)) -> c#(x1) -> c#(b(x1)) -> b#(c(x1)) 41.16/10.72 a#(a(x1)) -> c#(x1) -> c#(b(x1)) -> c#(x1) 41.16/10.72 SCC Processor: 41.16/10.72 #sccs: 1 41.16/10.72 #rules: 3 41.16/10.72 #arcs: 8/25 41.16/10.72 DPs: 41.16/10.72 c#(b(x1)) -> c#(x1) 41.16/10.72 c#(b(x1)) -> a#(b(c(x1))) 41.16/10.72 a#(a(x1)) -> c#(x1) 41.16/10.72 TRS: 41.16/10.72 a(x1) -> x1 41.16/10.72 a(a(x1)) -> b(c(x1)) 41.16/10.72 b(x1) -> x1 41.16/10.72 c(x1) -> x1 41.16/10.72 c(b(x1)) -> a(b(c(x1))) 41.16/10.72 Root-Labeling Processor: 41.16/10.72 DPs: 41.16/10.72 c{#,(f6)}(f6(b)(b(f6)(x1))) -> c{#,(f6)}(f6(f6)(x1)) 41.16/10.72 c{#,(f6)}(f6(b)(b(a)(x1))) -> c{#,(f6)}(f6(a)(x1)) 41.16/10.72 c{#,(f6)}(f6(b)(b(b)(x1))) -> c{#,(f6)}(f6(b)(x1)) 41.16/10.72 c{#,(f6)}(f6(b)(b(c)(x1))) -> c{#,(f6)}(f6(c)(x1)) 41.16/10.72 c{#,(f6)}(f6(b)(b(f6)(x1))) -> a{#,(f6)}(f6(b)(b(c)(c(f6)(x1)))) 41.16/10.72 c{#,(f6)}(f6(b)(b(a)(x1))) -> a{#,(f6)}(f6(b)(b(c)(c(a)(x1)))) 41.16/10.72 c{#,(f6)}(f6(b)(b(b)(x1))) -> a{#,(f6)}(f6(b)(b(c)(c(b)(x1)))) 41.16/10.72 c{#,(f6)}(f6(b)(b(c)(x1))) -> a{#,(f6)}(f6(b)(b(c)(c(c)(x1)))) 41.16/10.72 a{#,(f6)}(f6(a)(a(f6)(x1))) -> c{#,(f6)}(f6(f6)(x1)) 41.16/10.72 a{#,(f6)}(f6(a)(a(a)(x1))) -> c{#,(f6)}(f6(a)(x1)) 41.16/10.72 a{#,(f6)}(f6(a)(a(b)(x1))) -> c{#,(f6)}(f6(b)(x1)) 41.16/10.72 a{#,(f6)}(f6(a)(a(c)(x1))) -> c{#,(f6)}(f6(c)(x1)) 41.16/10.72 TRS: 41.16/10.72 f6(a)(a(f6)(x1)) -> f6(f6)(x1) 41.16/10.72 f6(a)(a(a)(x1)) -> f6(a)(x1) 41.16/10.72 f6(a)(a(b)(x1)) -> f6(b)(x1) 41.16/10.72 f6(a)(a(c)(x1)) -> f6(c)(x1) 41.16/10.72 a(a)(a(f6)(x1)) -> a(f6)(x1) 41.16/10.72 a(a)(a(a)(x1)) -> a(a)(x1) 41.16/10.72 a(a)(a(b)(x1)) -> a(b)(x1) 41.16/10.72 a(a)(a(c)(x1)) -> a(c)(x1) 41.16/10.72 b(a)(a(f6)(x1)) -> b(f6)(x1) 41.16/10.72 b(a)(a(a)(x1)) -> b(a)(x1) 41.16/10.72 b(a)(a(b)(x1)) -> b(b)(x1) 41.16/10.72 b(a)(a(c)(x1)) -> b(c)(x1) 41.16/10.72 c(a)(a(f6)(x1)) -> c(f6)(x1) 41.16/10.72 c(a)(a(a)(x1)) -> c(a)(x1) 41.16/10.72 c(a)(a(b)(x1)) -> c(b)(x1) 41.16/10.72 c(a)(a(c)(x1)) -> c(c)(x1) 41.16/10.72 f6(a)(a(a)(a(f6)(x1))) -> f6(b)(b(c)(c(f6)(x1))) 41.16/10.72 f6(a)(a(a)(a(a)(x1))) -> f6(b)(b(c)(c(a)(x1))) 41.16/10.72 f6(a)(a(a)(a(b)(x1))) -> f6(b)(b(c)(c(b)(x1))) 41.16/10.72 f6(a)(a(a)(a(c)(x1))) -> f6(b)(b(c)(c(c)(x1))) 41.16/10.72 a(a)(a(a)(a(f6)(x1))) -> a(b)(b(c)(c(f6)(x1))) 41.16/10.72 a(a)(a(a)(a(a)(x1))) -> a(b)(b(c)(c(a)(x1))) 41.16/10.72 a(a)(a(a)(a(b)(x1))) -> a(b)(b(c)(c(b)(x1))) 41.16/10.72 a(a)(a(a)(a(c)(x1))) -> a(b)(b(c)(c(c)(x1))) 41.16/10.72 b(a)(a(a)(a(f6)(x1))) -> b(b)(b(c)(c(f6)(x1))) 41.16/10.72 b(a)(a(a)(a(a)(x1))) -> b(b)(b(c)(c(a)(x1))) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS_Standard 2019-03-29 03.29