details

property	value
status	complete
benchmark	size-12-alpha-3-num-493.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n129.star.cs.uiowa.edu
space	Waldmann_07_size12

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	23.1822 seconds
cpu usage	88.0368
user time	85.8523
system time	2.18449
max virtual memory	5.9815728E7
max residence set size	4795240.0

stage attributes

key	value
starexec-result	NO

output

87.72/23.13 NO 87.72/23.14 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 87.72/23.14 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 87.72/23.14 87.72/23.14 87.72/23.14 Termination w.r.t. Q of the given QTRS could be disproven: 87.72/23.14 87.72/23.14 (0) QTRS 87.72/23.14 (1) NonTerminationProof [COMPLETE, 3677 ms] 87.72/23.14 (2) NO 87.72/23.14 87.72/23.14 87.72/23.14 ---------------------------------------- 87.72/23.14 87.72/23.14 (0) 87.72/23.14 Obligation: 87.72/23.14 Q restricted rewrite system: 87.72/23.14 The TRS R consists of the following rules: 87.72/23.14 87.72/23.14 a(a(x1)) -> b(x1) 87.72/23.14 b(a(c(x1))) -> c(c(a(a(a(a(x1)))))) 87.72/23.14 87.72/23.14 Q is empty. 87.72/23.14 87.72/23.14 ---------------------------------------- 87.72/23.14 87.72/23.14 (1) NonTerminationProof (COMPLETE) 87.72/23.14 We used the non-termination processor [OPPELT08] to show that the SRS problem is infinite. 87.72/23.14 87.72/23.14 Found the self-embedding DerivationStructure: 87.72/23.14 "b a c a a c c a c c -> c c c c a c c b c c a b a c a a c c a c c a a a a" 87.72/23.14 b a c a a c c a c c -> c c c c a c c b c c a b a c a a c c a c c a a a a 87.72/23.14 by OverlapClosure OC 2"b a c a a c c a c -> c c c c a c c b c c a b a c a a c c a b a 87.72/23.14 by OverlapClosure OC 2"b a c a a c c -> c c c c a c c b c c a b a c a a b 87.72/23.14 by OverlapClosure OC 3"b a c a a c c -> c c c c a c c b c c a a a a c a a b 87.72/23.14 by OverlapClosure OC 3"b a c a a c c -> c c c c a c c b b a c c a a b 87.72/23.14 by OverlapClosure OC 2"b a c a a c -> c c c c a c c b b a b a 87.72/23.14 by OverlapClosure OC 3"b a c a a c -> c c c c a b a c a b a 87.72/23.14 by OverlapClosure OC 3"b a c a a c -> c c c c a a a a c a b a 87.72/23.14 by OverlapClosure OC 3"b a c a a c -> c c b a c c a b a 87.72/23.14 by OverlapClosure OC 2"b a c -> c c b a a 87.72/23.14 by OverlapClosure OC 3"b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)""a a -> b 87.72/23.14 by original rule (OC 1)"""a a a c -> c c a b a 87.72/23.14 by OverlapClosure OC 3"a a a c -> c c a a a a 87.72/23.14 by OverlapClosure OC 2"a a -> b 87.72/23.14 by original rule (OC 1)""b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)"""a a -> b 87.72/23.14 by original rule (OC 1)""""b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)"""a a -> b 87.72/23.14 by original rule (OC 1)"""b a c -> c c b b 87.72/23.14 by OverlapClosure OC 3"b a c -> c c a a b 87.72/23.14 by OverlapClosure OC 2"b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)""a a -> b 87.72/23.14 by original rule (OC 1)"""a a -> b 87.72/23.14 by original rule (OC 1)""""b a c -> c c a a b 87.72/23.14 by OverlapClosure OC 2"b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)""a a -> b 87.72/23.14 by original rule (OC 1)""""b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)"""a a -> b 87.72/23.14 by original rule (OC 1)"""b a c -> c c a b a 87.72/23.14 by OverlapClosure OC 3"b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)""a a -> b 87.72/23.14 by original rule (OC 1)""""b a c -> c c a a a a 87.72/23.14 by original rule (OC 1)" 87.72/23.14 87.72/23.14 ---------------------------------------- 87.72/23.14 87.72/23.14 (2) 87.72/23.14 NO 88.00/23.18 EOF popout

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job log

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actions

all output return to SRS_Standard 2019-03-29 03.29