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SRS_Standard 2019-03-29 03.29 pair #432290972
details
property
value
status
complete
benchmark
size-12-alpha-3-num-45.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n180.star.cs.uiowa.edu
space
Waldmann_07_size12
run statistics
property
value
solver
matchbox-2019-03-17
configuration
std.sh
runtime (wallclock)
13.7508 seconds
cpu usage
105.993
user time
88.565
system time
17.4276
max virtual memory
1.16819596E8
max residence set size
935104.0
stage attributes
key
value
starexec-result
YES
output
50.31/13.00 YES 50.31/13.00 property Termination 50.31/13.00 has value True 50.31/13.00 for SRS ( [a] -> [], [a] -> [b, c], [b, b] -> [a, a], [c, c, c] -> [b]) 50.31/13.00 reason 50.31/13.00 remap for 4 rules 50.31/13.00 property Termination 50.31/13.01 has value True 50.31/13.01 for SRS ( [0] -> [], [0] -> [1, 2], [1, 1] -> [0, 0], [2, 2, 2] -> [1]) 50.31/13.01 reason 50.31/13.01 reverse each lhs and rhs 50.31/13.01 property Termination 50.31/13.01 has value True 50.31/13.01 for SRS ( [0] -> [], [0] -> [2, 1], [1, 1] -> [0, 0], [2, 2, 2] -> [1]) 50.31/13.01 reason 50.31/13.01 DP transform 50.36/13.01 property Termination 50.36/13.01 has value True 50.36/13.01 for SRS ( [0] ->= [], [0] ->= [2, 1], [1, 1] ->= [0, 0], [2, 2, 2] ->= [1], [0#] |-> [2#, 1], [0#] |-> [1#], [1#, 1] |-> [0#, 0], [1#, 1] |-> [0#], [2#, 2, 2] |-> [1#]) 50.36/13.01 reason 50.36/13.01 remap for 9 rules 50.36/13.01 property Termination 50.36/13.01 has value True 50.36/13.02 for SRS ( [0] ->= [], [0] ->= [1, 2], [2, 2] ->= [0, 0], [1, 1, 1] ->= [2], [3] |-> [4, 2], [3] |-> [5], [5, 2] |-> [3, 0], [5, 2] |-> [3], [4, 1, 1] |-> [5]) 50.36/13.02 reason 50.36/13.02 EDG has 1 SCCs 50.36/13.02 property Termination 50.36/13.02 has value True 50.36/13.02 for SRS ( [3] |-> [4, 2], [4, 1, 1] |-> [5], [5, 2] |-> [3], [3] |-> [5], [5, 2] |-> [3, 0], [0] ->= [], [0] ->= [1, 2], [2, 2] ->= [0, 0], [1, 1, 1] ->= [2]) 50.36/13.02 reason 50.36/13.02 Matrix { monotone = Weak, domain = Arctic, bits = 3, dim = 4, solver = Minisatapi, verbose = False, tracing = False} 50.36/13.02 interpretation 50.36/13.02 0 Wk / 0A 3A 3A 3A \ 50.36/13.02 | - 0A 0A 0A | 50.36/13.02 | - 0A 0A 0A | 50.36/13.02 \ - - - 0A / 50.36/13.02 1 Wk / 3A 0A 0A 1A \ 50.36/13.02 | 0A - - - | 50.36/13.02 | 0A - - - | 50.36/13.02 \ - - - 0A / 50.36/13.03 2 Wk / - 0A 0A 0A \ 50.36/13.03 | 0A 2A 0A 2A | 50.36/13.03 | - 3A 3A 3A | 50.36/13.03 \ - - - 0A / 50.36/13.03 3 Wk / 4A 6A 6A 3A \ 50.36/13.03 | - - - - | 50.36/13.03 | 0A 2A 1A 3A | 50.36/13.03 \ - - - 0A / 50.36/13.03 4 Wk / 1A - 0A - \ 50.36/13.03 | - - - - | 50.36/13.03 | - 0A - 3A | 50.36/13.03 \ - - - 0A / 50.36/13.03 5 Wk / 2A 4A 4A - \ 50.36/13.03 | - - - - | 50.36/13.03 | - 0A 0A 0A | 50.36/13.03 \ - - - 0A / 50.36/13.03 [3] |-> [4, 2] 50.36/13.04 lhs rhs ge gt 50.36/13.04 Wk / 4A 6A 6A 3A \ Wk / - 3A 3A 3A \ True False 50.36/13.04 | - - - - | | - - - - | 50.36/13.04 | 0A 2A 1A 3A | | 0A 2A 0A 3A | 50.36/13.04 \ - - - 0A / \ - - - 0A / 50.36/13.04 [4, 1, 1] |-> [5] 50.36/13.05 lhs rhs ge gt 50.36/13.05 Wk / 7A 4A 4A 5A \ Wk / 2A 4A 4A - \ True False 50.36/13.05 | - - - - | | - - - - | 50.36/13.05 | 3A 0A 0A 3A | | - 0A 0A 0A | 50.36/13.05 \ - - - 0A / \ - - - 0A / 50.36/13.05 [5, 2] |-> [3] 50.36/13.05 lhs rhs ge gt 50.36/13.05 Wk / 4A 7A 7A 7A \ Wk / 4A 6A 6A 3A \ True False 50.36/13.05 | - - - - | | - - - - | 50.36/13.05 | 0A 3A 3A 3A | | 0A 2A 1A 3A | 50.36/13.05 \ - - - 0A / \ - - - 0A / 50.36/13.05 [3] |-> [5] 50.36/13.09 lhs rhs ge gt 50.36/13.09 Wk / 4A 6A 6A 3A \ Wk / 2A 4A 4A - \ True True 50.36/13.09 | - - - - | | - - - - | 50.36/13.09 | 0A 2A 1A 3A | | - 0A 0A 0A | 50.36/13.09 \ - - - 0A / \ - - - 0A / 50.36/13.09 [5, 2] |-> [3, 0] 50.91/13.23 lhs rhs ge gt 50.91/13.23 Wk / 4A 7A 7A 7A \ Wk / 4A 7A 7A 7A \ True False 50.91/13.23 | - - - - | | - - - - | 50.91/13.23 | 0A 3A 3A 3A | | 0A 3A 3A 3A | 50.91/13.23 \ - - - 0A / \ - - - 0A / 50.91/13.23 [0] ->= [] 50.91/13.24 lhs rhs ge gt 50.91/13.24 Wk / 0A 3A 3A 3A \ Wk / 0A - - - \ True False 50.91/13.24 | - 0A 0A 0A | | - 0A - - | 50.91/13.24 | - 0A 0A 0A | | - - 0A - | 50.91/13.24 \ - - - 0A / \ - - - 0A / 50.91/13.24 [0] ->= [1, 2] 50.91/13.24 lhs rhs ge gt 50.91/13.24 Wk / 0A 3A 3A 3A \ Wk / 0A 3A 3A 3A \ True False 50.91/13.24 | - 0A 0A 0A | | - 0A 0A 0A | 50.91/13.24 | - 0A 0A 0A | | - 0A 0A 0A | 50.91/13.24 \ - - - 0A / \ - - - 0A / 50.91/13.24 [2, 2] ->= [0, 0] 50.91/13.24 lhs rhs ge gt
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