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SRS_Standard 2019-03-29 03.29 pair #432291872
details
property
value
status
complete
benchmark
z083.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n138.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
matchbox-2019-03-17
configuration
std.sh
runtime (wallclock)
12.6171 seconds
cpu usage
49.5678
user time
43.4973
system time
6.07054
max virtual memory
1.16825744E8
max residence set size
1148404.0
stage attributes
key
value
starexec-result
YES
output
44.78/11.34 YES 44.78/11.34 property Termination 44.78/11.34 has value True 44.78/11.36 for SRS ( [b, d, b] -> [c, d, b], [b, a, c] -> [b, c], [a, d] -> [d, c], [b, b, b] -> [a, b, c], [d, c] -> [b, d], [d, c] -> [d, b, d], [d, a, c] -> [b, b]) 44.78/11.36 reason 44.78/11.37 remap for 7 rules 44.78/11.37 property Termination 44.78/11.37 has value True 44.78/11.37 for SRS ( [0, 1, 0] -> [2, 1, 0], [0, 3, 2] -> [0, 2], [3, 1] -> [1, 2], [0, 0, 0] -> [3, 0, 2], [1, 2] -> [0, 1], [1, 2] -> [1, 0, 1], [1, 3, 2] -> [0, 0]) 44.78/11.37 reason 44.78/11.37 weights 44.78/11.37 Map [(0, 1/1), (2, 1/1), (3, 1/1)] 44.78/11.37 44.78/11.37 property Termination 44.78/11.38 has value True 44.78/11.38 for SRS ( [0, 1, 0] -> [2, 1, 0], [3, 1] -> [1, 2], [0, 0, 0] -> [3, 0, 2], [1, 2] -> [0, 1], [1, 2] -> [1, 0, 1], [1, 3, 2] -> [0, 0]) 44.78/11.38 reason 44.78/11.38 reverse each lhs and rhs 44.78/11.38 property Termination 44.78/11.38 has value True 44.78/11.39 for SRS ( [0, 1, 0] -> [0, 1, 2], [1, 3] -> [2, 1], [0, 0, 0] -> [2, 0, 3], [2, 1] -> [1, 0], [2, 1] -> [1, 0, 1], [2, 3, 1] -> [0, 0]) 44.78/11.39 reason 44.78/11.39 DP transform 44.78/11.39 property Termination 44.78/11.39 has value True 44.78/11.39 for SRS ( [0, 1, 0] ->= [0, 1, 2], [1, 3] ->= [2, 1], [0, 0, 0] ->= [2, 0, 3], [2, 1] ->= [1, 0], [2, 1] ->= [1, 0, 1], [2, 3, 1] ->= [0, 0], [0#, 1, 0] |-> [0#, 1, 2], [0#, 1, 0] |-> [1#, 2], [0#, 1, 0] |-> [2#], [1#, 3] |-> [2#, 1], [1#, 3] |-> [1#], [0#, 0, 0] |-> [2#, 0, 3], [0#, 0, 0] |-> [0#, 3], [2#, 1] |-> [1#, 0], [2#, 1] |-> [0#], [2#, 1] |-> [1#, 0, 1], [2#, 1] |-> [0#, 1], [2#, 3, 1] |-> [0#, 0], [2#, 3, 1] |-> [0#]) 44.78/11.39 reason 44.78/11.39 remap for 19 rules 44.78/11.39 property Termination 44.78/11.39 has value True 44.78/11.39 for SRS ( [0, 1, 0] ->= [0, 1, 2], [1, 3] ->= [2, 1], [0, 0, 0] ->= [2, 0, 3], [2, 1] ->= [1, 0], [2, 1] ->= [1, 0, 1], [2, 3, 1] ->= [0, 0], [4, 1, 0] |-> [4, 1, 2], [4, 1, 0] |-> [5, 2], [4, 1, 0] |-> [6], [5, 3] |-> [6, 1], [5, 3] |-> [5], [4, 0, 0] |-> [6, 0, 3], [4, 0, 0] |-> [4, 3], [6, 1] |-> [5, 0], [6, 1] |-> [4], [6, 1] |-> [5, 0, 1], [6, 1] |-> [4, 1], [6, 3, 1] |-> [4, 0], [6, 3, 1] |-> [4]) 44.78/11.39 reason 44.78/11.39 weights 44.78/11.39 Map [(0, 1/5), (2, 1/5), (3, 1/5), (4, 1/5), (6, 1/5)] 44.78/11.39 44.78/11.39 property Termination 44.78/11.39 has value True 45.13/11.41 for SRS ( [0, 1, 0] ->= [0, 1, 2], [1, 3] ->= [2, 1], [0, 0, 0] ->= [2, 0, 3], [2, 1] ->= [1, 0], [2, 1] ->= [1, 0, 1], [2, 3, 1] ->= [0, 0], [4, 1, 0] |-> [4, 1, 2], [5, 3] |-> [6, 1], [4, 0, 0] |-> [6, 0, 3], [6, 1] |-> [5, 0], [6, 1] |-> [4], [6, 1] |-> [5, 0, 1], [6, 1] |-> [4, 1], [6, 3, 1] |-> [4, 0]) 45.13/11.41 reason 45.13/11.41 EDG has 2 SCCs 45.13/11.41 property Termination 45.13/11.41 has value True 45.13/11.42 for SRS ( [4, 1, 0] |-> [4, 1, 2], [0, 1, 0] ->= [0, 1, 2], [1, 3] ->= [2, 1], [0, 0, 0] ->= [2, 0, 3], [2, 1] ->= [1, 0], [2, 1] ->= [1, 0, 1], [2, 3, 1] ->= [0, 0]) 45.13/11.42 reason 45.13/11.42 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 5, solver = Minisatapi, verbose = False, tracing = True} 45.13/11.42 interpretation 45.13/11.42 0 / 15A 15A 15A 15A 15A \ 45.13/11.42 | 15A 15A 15A 15A 15A | 45.13/11.42 | 10A 15A 15A 15A 15A | 45.13/11.42 | 10A 15A 15A 15A 15A | 45.13/11.42 \ 10A 10A 15A 15A 15A / 45.13/11.42 1 / 0A 0A 0A 0A 0A \ 45.13/11.42 | 0A 0A 0A 0A 0A | 45.13/11.42 | 0A 0A 0A 0A 0A | 45.13/11.42 | -5A -5A -5A -5A 0A | 45.13/11.42 \ -5A -5A -5A -5A -5A / 45.13/11.42 2 / 10A 10A 15A 15A 15A \ 45.13/11.42 | 10A 10A 15A 15A 15A | 45.13/11.42 | 10A 10A 15A 15A 15A | 45.13/11.42 | 10A 10A 15A 15A 15A | 45.13/11.42 \ 10A 10A 10A 10A 10A / 45.13/11.42 3 / 20A 20A 20A 20A 20A \ 45.13/11.42 | 15A 15A 15A 15A 15A | 45.13/11.42 | 15A 15A 15A 15A 15A | 45.13/11.42 | 15A 15A 15A 15A 15A | 45.13/11.42 \ 15A 15A 15A 15A 15A / 45.13/11.42 4 / 18A 18A 19A 21A 21A \ 45.13/11.42 | 18A 18A 19A 21A 21A | 45.13/11.42 | 18A 18A 19A 21A 21A | 45.13/11.42 | 18A 18A 19A 21A 21A | 45.13/11.42 \ 18A 18A 19A 21A 21A / 45.13/11.42 [4, 1, 0] |-> [4, 1, 2] 45.13/11.42 lhs rhs ge gt 45.13/11.42 / 34A 34A 36A 36A 36A \ / 31A 31A 34A 34A 34A \ True True 45.13/11.42 | 34A 34A 36A 36A 36A | | 31A 31A 34A 34A 34A | 45.13/11.42 | 34A 34A 36A 36A 36A | | 31A 31A 34A 34A 34A | 45.13/11.42 | 34A 34A 36A 36A 36A | | 31A 31A 34A 34A 34A | 45.13/11.42 \ 34A 34A 36A 36A 36A / \ 31A 31A 34A 34A 34A / 45.13/11.42 [0, 1, 0] ->= [0, 1, 2] 45.13/11.42 lhs rhs ge gt 45.13/11.42 / 30A 30A 30A 30A 30A \ / 25A 25A 30A 30A 30A \ True False 45.13/11.42 | 30A 30A 30A 30A 30A | | 25A 25A 30A 30A 30A | 45.13/11.42 | 30A 30A 30A 30A 30A | | 25A 25A 30A 30A 30A | 45.13/11.42 | 30A 30A 30A 30A 30A | | 25A 25A 30A 30A 30A | 45.13/11.42 \ 30A 30A 30A 30A 30A / \ 25A 25A 30A 30A 30A / 45.13/11.42 [1, 3] ->= [2, 1] 45.13/11.42 lhs rhs ge gt 45.13/11.42 / 20A 20A 20A 20A 20A \ / 15A 15A 15A 15A 15A \ True False 45.13/11.42 | 20A 20A 20A 20A 20A | | 15A 15A 15A 15A 15A | 45.13/11.42 | 20A 20A 20A 20A 20A | | 15A 15A 15A 15A 15A | 45.13/11.42 | 15A 15A 15A 15A 15A | | 15A 15A 15A 15A 15A | 45.13/11.42 \ 15A 15A 15A 15A 15A / \ 10A 10A 10A 10A 10A / 45.13/11.42 [0, 0, 0] ->= [2, 0, 3] 45.13/11.42 lhs rhs ge gt 45.13/11.42 / 45A 45A 45A 45A 45A \ / 45A 45A 45A 45A 45A \ True False 45.13/11.42 | 45A 45A 45A 45A 45A | | 45A 45A 45A 45A 45A | 45.13/11.42 | 45A 45A 45A 45A 45A | | 45A 45A 45A 45A 45A | 45.13/11.42 | 45A 45A 45A 45A 45A | | 45A 45A 45A 45A 45A | 45.13/11.42 \ 45A 45A 45A 45A 45A / \ 45A 45A 45A 45A 45A / 45.13/11.42 [2, 1] ->= [1, 0]
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