details

property	value
status	complete
benchmark	z033.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n100.star.cs.uiowa.edu
space	Zantema_04

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.71576 seconds
cpu usage	3.65014
user time	3.48167
system time	0.168471
max virtual memory	1.901082E7
max residence set size	288136.0

stage attributes

key	value
starexec-result	YES

output

3.20/1.66 YES 3.56/1.67 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 3.56/1.67 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 3.56/1.67 3.56/1.67 3.56/1.67 Termination w.r.t. Q of the given QTRS could be proven: 3.56/1.67 3.56/1.67 (0) QTRS 3.56/1.67 (1) RFCMatchBoundsTRSProof [EQUIVALENT, 9 ms] 3.56/1.67 (2) YES 3.56/1.67 3.56/1.67 3.56/1.67 ---------------------------------------- 3.56/1.67 3.56/1.67 (0) 3.56/1.67 Obligation: 3.56/1.67 Q restricted rewrite system: 3.56/1.67 The TRS R consists of the following rules: 3.56/1.67 3.56/1.67 b(a(b(b(a(b(a(x1))))))) -> a(b(a(a(b(b(a(b(b(a(x1)))))))))) 3.56/1.67 3.56/1.67 Q is empty. 3.56/1.67 3.56/1.67 ---------------------------------------- 3.56/1.67 3.56/1.67 (1) RFCMatchBoundsTRSProof (EQUIVALENT) 3.56/1.67 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. 3.56/1.67 The following rules were used to construct the certificate: 3.56/1.67 3.56/1.67 b(a(b(b(a(b(a(x1))))))) -> a(b(a(a(b(b(a(b(b(a(x1)))))))))) 3.56/1.67 3.56/1.67 The certificate found is represented by the following graph. 3.56/1.67 The certificate consists of the following enumerated nodes: 3.56/1.67 1, 5, 7, 16, 17, 18, 19, 20, 21, 22, 23, 41, 42, 43, 44, 45, 46, 47, 48, 49 3.56/1.67 3.56/1.67 Node 1 is start node and node 5 is final node. 3.56/1.67 3.56/1.67 Those nodes are connected through the following edges: 3.56/1.67 3.56/1.67 * 1 to 7 labelled a_1(0)* 5 to 5 labelled #_1(0)* 7 to 16 labelled b_1(0)* 16 to 17 labelled a_1(0)* 17 to 18 labelled a_1(0)* 18 to 19 labelled b_1(0)* 19 to 20 labelled b_1(0)* 19 to 41 labelled a_1(1)* 20 to 21 labelled a_1(0)* 21 to 22 labelled b_1(0)* 22 to 23 labelled b_1(0)* 22 to 41 labelled a_1(1)* 23 to 5 labelled a_1(0)* 41 to 42 labelled b_1(1)* 42 to 43 labelled a_1(1)* 43 to 44 labelled a_1(1)* 44 to 45 labelled b_1(1)* 45 to 46 labelled b_1(1)* 45 to 41 labelled a_1(1)* 46 to 47 labelled a_1(1)* 47 to 48 labelled b_1(1)* 48 to 49 labelled b_1(1)* 48 to 41 labelled a_1(1)* 49 to 5 labelled a_1(1) 3.56/1.67 3.56/1.67 3.56/1.67 ---------------------------------------- 3.56/1.67 3.56/1.67 (2) 3.56/1.67 YES 3.63/1.71 EOF popout

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all output return to SRS_Standard 2019-03-29 03.29