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SRS_Standard 2019-03-29 03.29 pair #432292346
details
property
value
status
complete
benchmark
z110.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n057.star.cs.uiowa.edu
space
Zantema_04
run statistics
property
value
solver
matchbox-2019-03-17
configuration
std.sh
runtime (wallclock)
16.7551 seconds
cpu usage
66.2682
user time
57.1149
system time
9.15331
max virtual memory
1.16691496E8
max residence set size
1059096.0
stage attributes
key
value
starexec-result
YES
output
63.69/16.10 YES 63.69/16.10 property Termination 63.69/16.10 has value True 63.69/16.14 for SRS ( [a, a] -> [b], [b, a] -> [a, b], [b, b, c] -> [c, a], [b, b] -> [a, a, a], [c, a] -> [b, a, c]) 63.69/16.14 reason 63.69/16.14 remap for 5 rules 63.69/16.14 property Termination 63.69/16.14 has value True 64.04/16.17 for SRS ( [0, 0] -> [1], [1, 0] -> [0, 1], [1, 1, 2] -> [2, 0], [1, 1] -> [0, 0, 0], [2, 0] -> [1, 0, 2]) 64.04/16.17 reason 64.04/16.18 reverse each lhs and rhs 64.04/16.18 property Termination 64.04/16.18 has value True 64.16/16.21 for SRS ( [0, 0] -> [1], [0, 1] -> [1, 0], [2, 1, 1] -> [0, 2], [1, 1] -> [0, 0, 0], [0, 2] -> [2, 0, 1]) 64.16/16.21 reason 64.16/16.21 DP transform 64.16/16.21 property Termination 64.16/16.21 has value True 64.16/16.22 for SRS ( [0, 0] ->= [1], [0, 1] ->= [1, 0], [2, 1, 1] ->= [0, 2], [1, 1] ->= [0, 0, 0], [0, 2] ->= [2, 0, 1], [0#, 0] |-> [1#], [0#, 1] |-> [1#, 0], [0#, 1] |-> [0#], [2#, 1, 1] |-> [0#, 2], [2#, 1, 1] |-> [2#], [1#, 1] |-> [0#, 0, 0], [1#, 1] |-> [0#, 0], [1#, 1] |-> [0#], [0#, 2] |-> [2#, 0, 1], [0#, 2] |-> [0#, 1], [0#, 2] |-> [1#]) 64.16/16.22 reason 64.16/16.22 remap for 16 rules 64.16/16.22 property Termination 64.16/16.22 has value True 64.33/16.23 for SRS ( [0, 0] ->= [1], [0, 1] ->= [1, 0], [2, 1, 1] ->= [0, 2], [1, 1] ->= [0, 0, 0], [0, 2] ->= [2, 0, 1], [3, 0] |-> [4], [3, 1] |-> [4, 0], [3, 1] |-> [3], [5, 1, 1] |-> [3, 2], [5, 1, 1] |-> [5], [4, 1] |-> [3, 0, 0], [4, 1] |-> [3, 0], [4, 1] |-> [3], [3, 2] |-> [5, 0, 1], [3, 2] |-> [3, 1], [3, 2] |-> [4]) 64.33/16.23 reason 64.33/16.23 weights 64.33/16.23 Map [(2, 1/2), (5, 1/2)] 64.33/16.23 64.33/16.23 property Termination 64.33/16.23 has value True 64.33/16.23 for SRS ( [0, 0] ->= [1], [0, 1] ->= [1, 0], [2, 1, 1] ->= [0, 2], [1, 1] ->= [0, 0, 0], [0, 2] ->= [2, 0, 1], [3, 0] |-> [4], [3, 1] |-> [4, 0], [3, 1] |-> [3], [5, 1, 1] |-> [3, 2], [5, 1, 1] |-> [5], [4, 1] |-> [3, 0, 0], [4, 1] |-> [3, 0], [4, 1] |-> [3], [3, 2] |-> [5, 0, 1]) 64.33/16.23 reason 64.33/16.23 EDG has 1 SCCs 64.33/16.23 property Termination 64.33/16.23 has value True 64.33/16.24 for SRS ( [3, 0] |-> [4], [4, 1] |-> [3], [3, 2] |-> [5, 0, 1], [5, 1, 1] |-> [5], [5, 1, 1] |-> [3, 2], [3, 1] |-> [3], [3, 1] |-> [4, 0], [4, 1] |-> [3, 0], [4, 1] |-> [3, 0, 0], [0, 0] ->= [1], [0, 1] ->= [1, 0], [2, 1, 1] ->= [0, 2], [1, 1] ->= [0, 0, 0], [0, 2] ->= [2, 0, 1]) 64.33/16.24 reason 64.33/16.24 Matrix { monotone = Weak, domain = Natural, bits = 3, dim = 4, solver = Minisatapi, verbose = False, tracing = False} 64.33/16.24 interpretation 64.37/16.24 0 Wk / 1 0 1 0 \ 64.37/16.24 | 1 1 0 1 | 64.37/16.24 | 0 0 0 0 | 64.37/16.24 \ 0 0 0 1 / 64.37/16.24 1 Wk / 1 0 1 0 \ 64.37/16.24 | 2 1 1 2 | 64.37/16.24 | 0 0 0 0 | 64.37/16.24 \ 0 0 0 1 / 64.37/16.24 2 Wk / 3 0 2 2 \ 64.37/16.24 | 0 1 0 2 | 64.37/16.24 | 0 0 1 0 | 64.37/16.25 \ 0 0 0 1 / 64.37/16.25 3 Wk / 1 1 0 2 \ 64.37/16.25 | 0 0 0 2 | 64.37/16.25 | 0 0 0 4 | 64.37/16.25 \ 0 0 0 1 / 64.37/16.25 4 Wk / 1 1 0 2 \ 64.37/16.25 | 0 0 0 2 | 64.37/16.25 | 0 0 0 4 | 64.37/16.25 \ 0 0 0 1 / 64.37/16.25 5 Wk / 0 1 0 2 \ 64.37/16.25 | 0 0 0 2 | 64.37/16.25 | 0 0 0 4 | 64.37/16.26 \ 0 0 0 1 / 64.37/16.26 [3, 0] |-> [4] 64.37/16.28 lhs rhs ge gt 64.37/16.29 Wk / 2 1 1 3 \ Wk / 1 1 0 2 \ True True 64.37/16.29 | 0 0 0 2 | | 0 0 0 2 | 64.37/16.29 | 0 0 0 4 | | 0 0 0 4 | 64.37/16.29 \ 0 0 0 1 / \ 0 0 0 1 / 64.37/16.29 [4, 1] |-> [3] 64.65/16.31 lhs rhs ge gt 64.65/16.31 Wk / 3 1 2 4 \ Wk / 1 1 0 2 \ True True 64.65/16.31 | 0 0 0 2 | | 0 0 0 2 | 64.65/16.32 | 0 0 0 4 | | 0 0 0 4 | 64.65/16.32 \ 0 0 0 1 / \ 0 0 0 1 / 64.65/16.32 [3, 2] |-> [5, 0, 1] 64.65/16.32 lhs rhs ge gt 64.65/16.32 Wk / 3 1 2 6 \ Wk / 3 1 2 5 \ True True 64.65/16.32 | 0 0 0 2 | | 0 0 0 2 | 64.65/16.32 | 0 0 0 4 | | 0 0 0 4 | 64.65/16.32 \ 0 0 0 1 / \ 0 0 0 1 / 64.65/16.32 [5, 1, 1] |-> [5] 64.65/16.32 lhs rhs ge gt 64.65/16.32 Wk / 4 1 3 6 \ Wk / 0 1 0 2 \ True True 64.65/16.32 | 0 0 0 2 | | 0 0 0 2 | 64.65/16.32 | 0 0 0 4 | | 0 0 0 4 | 64.65/16.32 \ 0 0 0 1 / \ 0 0 0 1 / 64.65/16.32 [5, 1, 1] |-> [3, 2] 64.65/16.36 lhs rhs ge gt 64.92/16.40 Wk / 4 1 3 6 \ Wk / 3 1 2 6 \ True False 64.92/16.40 | 0 0 0 2 | | 0 0 0 2 | 64.92/16.40 | 0 0 0 4 | | 0 0 0 4 | 64.92/16.40 \ 0 0 0 1 / \ 0 0 0 1 / 64.92/16.40 [3, 1] |-> [3] 64.92/16.40 lhs rhs ge gt 64.92/16.40 Wk / 3 1 2 4 \ Wk / 1 1 0 2 \ True True 64.92/16.40 | 0 0 0 2 | | 0 0 0 2 | 64.92/16.40 | 0 0 0 4 | | 0 0 0 4 | 64.92/16.40 \ 0 0 0 1 / \ 0 0 0 1 / 64.92/16.40 [3, 1] |-> [4, 0]
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