details

property	value
status	complete
benchmark	abaaaa-aaaaabaabab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n154.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.96717 seconds
cpu usage	4.3764
user time	4.17634
system time	0.200066
max virtual memory	1.9075328E7
max residence set size	382196.0

stage attributes

key	value
starexec-result	YES

output

4.07/1.91 YES 4.07/1.92 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 4.07/1.92 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 4.07/1.92 4.07/1.92 4.07/1.92 Termination w.r.t. Q of the given QTRS could be proven: 4.07/1.92 4.07/1.92 (0) QTRS 4.07/1.92 (1) QTRS Reverse [EQUIVALENT, 0 ms] 4.07/1.92 (2) QTRS 4.07/1.92 (3) Strip Symbols Proof [SOUND, 0 ms] 4.07/1.92 (4) QTRS 4.07/1.92 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 5 ms] 4.07/1.92 (6) YES 4.07/1.92 4.07/1.92 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (0) 4.07/1.92 Obligation: 4.07/1.92 Q restricted rewrite system: 4.07/1.92 The TRS R consists of the following rules: 4.07/1.92 4.07/1.92 a(b(a(a(a(a(x1)))))) -> a(a(a(a(a(b(a(a(b(a(b(x1))))))))))) 4.07/1.92 4.07/1.92 Q is empty. 4.07/1.92 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (1) QTRS Reverse (EQUIVALENT) 4.07/1.92 We applied the QTRS Reverse Processor [REVERSE]. 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (2) 4.07/1.92 Obligation: 4.07/1.92 Q restricted rewrite system: 4.07/1.92 The TRS R consists of the following rules: 4.07/1.92 4.07/1.92 a(a(a(a(b(a(x1)))))) -> b(a(b(a(a(b(a(a(a(a(a(x1))))))))))) 4.07/1.92 4.07/1.92 Q is empty. 4.07/1.92 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (3) Strip Symbols Proof (SOUND) 4.07/1.92 We were given the following TRS: 4.07/1.92 4.07/1.92 a(a(a(a(b(a(x1)))))) -> b(a(b(a(a(b(a(a(a(a(a(x1))))))))))) 4.07/1.92 4.07/1.92 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 4.07/1.92 4.07/1.92 a(a(a(a(b(x))))) -> b(a(b(a(a(b(a(a(a(a(x)))))))))) 4.07/1.92 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (4) 4.07/1.92 Obligation: 4.07/1.92 Q restricted rewrite system: 4.07/1.92 The TRS R consists of the following rules: 4.07/1.92 4.07/1.92 a(a(a(a(b(x))))) -> b(a(b(a(a(b(a(a(a(a(x)))))))))) 4.07/1.92 4.07/1.92 Q is empty. 4.07/1.92 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 4.07/1.92 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. 4.07/1.92 The following rules were used to construct the certificate: 4.07/1.92 4.07/1.92 a(a(a(a(b(x))))) -> b(a(b(a(a(b(a(a(a(a(x)))))))))) 4.07/1.92 4.07/1.92 The certificate found is represented by the following graph. 4.07/1.92 The certificate consists of the following enumerated nodes: 4.07/1.92 459, 460, 461, 462, 463, 464, 465, 466, 467, 468, 469, 480, 481, 482, 483, 484, 485, 486, 487, 488 4.07/1.92 4.07/1.92 Node 459 is start node and node 460 is final node. 4.07/1.92 4.07/1.92 Those nodes are connected through the following edges: 4.07/1.92 4.07/1.92 * 459 to 461 labelled b_1(0)* 460 to 460 labelled #_1(0)* 461 to 462 labelled a_1(0)* 462 to 463 labelled b_1(0)* 463 to 464 labelled a_1(0)* 464 to 465 labelled a_1(0)* 465 to 466 labelled b_1(0)* 466 to 467 labelled a_1(0)* 466 to 480 labelled b_1(1)* 467 to 468 labelled a_1(0)* 467 to 480 labelled b_1(1)* 468 to 469 labelled a_1(0)* 468 to 480 labelled b_1(1)* 469 to 460 labelled a_1(0)* 469 to 480 labelled b_1(1)* 480 to 481 labelled a_1(1)* 481 to 482 labelled b_1(1)* 482 to 483 labelled a_1(1)* 483 to 484 labelled a_1(1)* 484 to 485 labelled b_1(1)* 485 to 486 labelled a_1(1)* 485 to 480 labelled b_1(1)* 486 to 487 labelled a_1(1)* 486 to 480 labelled b_1(1)* 487 to 488 labelled a_1(1)* 487 to 480 labelled b_1(1)* 488 to 460 labelled a_1(1)* 488 to 480 labelled b_1(1) 4.07/1.92 4.07/1.92 4.07/1.92 ---------------------------------------- 4.07/1.92 4.07/1.92 (6) 4.07/1.92 YES 4.34/1.96 EOF popout

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