details

property	value
status	complete
benchmark	ababaabababa-aabababaababab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n119.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	2.54057 seconds
cpu usage	3.883
user time	3.72029
system time	0.162707
max virtual memory	1.8944252E7
max residence set size	298860.0

stage attributes

key	value
starexec-result	YES

output

3.72/1.70 YES 3.72/1.72 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 3.72/1.72 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 3.72/1.72 3.72/1.72 3.72/1.72 Termination w.r.t. Q of the given QTRS could be proven: 3.72/1.72 3.72/1.72 (0) QTRS 3.72/1.72 (1) QTRS Reverse [EQUIVALENT, 0 ms] 3.72/1.72 (2) QTRS 3.72/1.72 (3) Strip Symbols Proof [SOUND, 0 ms] 3.72/1.72 (4) QTRS 3.72/1.72 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] 3.72/1.72 (6) YES 3.72/1.72 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (0) 3.72/1.72 Obligation: 3.72/1.72 Q restricted rewrite system: 3.72/1.72 The TRS R consists of the following rules: 3.72/1.72 3.72/1.72 a(b(a(b(a(a(b(a(b(a(b(a(x1)))))))))))) -> a(a(b(a(b(a(b(a(a(b(a(b(a(b(x1)))))))))))))) 3.72/1.72 3.72/1.72 Q is empty. 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (1) QTRS Reverse (EQUIVALENT) 3.72/1.72 We applied the QTRS Reverse Processor [REVERSE]. 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (2) 3.72/1.72 Obligation: 3.72/1.72 Q restricted rewrite system: 3.72/1.72 The TRS R consists of the following rules: 3.72/1.72 3.72/1.72 a(b(a(b(a(b(a(a(b(a(b(a(x1)))))))))))) -> b(a(b(a(b(a(a(b(a(b(a(b(a(a(x1)))))))))))))) 3.72/1.72 3.72/1.72 Q is empty. 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (3) Strip Symbols Proof (SOUND) 3.72/1.72 We were given the following TRS: 3.72/1.72 3.72/1.72 a(b(a(b(a(b(a(a(b(a(b(a(x1)))))))))))) -> b(a(b(a(b(a(a(b(a(b(a(b(a(a(x1)))))))))))))) 3.72/1.72 3.72/1.72 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 3.72/1.72 3.72/1.72 a(b(a(b(a(b(a(a(b(a(b(x))))))))))) -> b(a(b(a(b(a(a(b(a(b(a(b(a(x))))))))))))) 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (4) 3.72/1.72 Obligation: 3.72/1.72 Q restricted rewrite system: 3.72/1.72 The TRS R consists of the following rules: 3.72/1.72 3.72/1.72 a(b(a(b(a(b(a(a(b(a(b(x))))))))))) -> b(a(b(a(b(a(a(b(a(b(a(b(a(x))))))))))))) 3.72/1.72 3.72/1.72 Q is empty. 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 3.72/1.72 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 2. This implies Q-termination of R. 3.72/1.72 The following rules were used to construct the certificate: 3.72/1.72 3.72/1.72 a(b(a(b(a(b(a(a(b(a(b(x))))))))))) -> b(a(b(a(b(a(a(b(a(b(a(b(a(x))))))))))))) 3.72/1.72 3.72/1.72 The certificate found is represented by the following graph. 3.72/1.72 The certificate consists of the following enumerated nodes: 3.72/1.72 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 434, 435, 436, 437, 438, 439, 440, 441, 442, 443, 444, 445 3.72/1.72 3.72/1.72 Node 344 is start node and node 345 is final node. 3.72/1.72 3.72/1.72 Those nodes are connected through the following edges: 3.72/1.72 3.72/1.72 * 344 to 346 labelled b_1(0)* 345 to 345 labelled #_1(0)* 346 to 347 labelled a_1(0)* 347 to 348 labelled b_1(0)* 348 to 349 labelled a_1(0)* 349 to 350 labelled b_1(0)* 350 to 351 labelled a_1(0)* 350 to 396 labelled b_1(1)* 351 to 352 labelled a_1(0)* 351 to 358 labelled b_1(1)* 352 to 353 labelled b_1(0)* 353 to 354 labelled a_1(0)* 353 to 358 labelled b_1(1)* 354 to 355 labelled b_1(0)* 355 to 356 labelled a_1(0)* 355 to 358 labelled b_1(1)* 356 to 357 labelled b_1(0)* 357 to 345 labelled a_1(0)* 357 to 358 labelled b_1(1)* 358 to 359 labelled a_1(1)* 359 to 360 labelled b_1(1)* 360 to 361 labelled a_1(1)* 361 to 362 labelled b_1(1)* 362 to 363 labelled a_1(1)* 362 to 434 labelled b_1(2)* 363 to 364 labelled a_1(1)* 363 to 358 labelled b_1(1)* 364 to 365 labelled b_1(1)* 365 to 366 labelled a_1(1)* 365 to 358 labelled b_1(1)* 366 to 367 labelled b_1(1)* 367 to 368 labelled a_1(1)* 367 to 358 labelled b_1(1)* 368 to 369 labelled b_1(1)* 369 to 345 labelled a_1(1)* 369 to 358 labelled b_1(1)* 396 to 397 labelled a_1(1)* 397 to 398 labelled b_1(1)* 398 to 399 labelled a_1(1)* 399 to 400 labelled b_1(1)* 400 to 401 labelled a_1(1)* 400 to 434 labelled b_1(2)* 401 to 402 labelled a_1(1)* 401 to 358 labelled b_1(1)* 402 to 403 labelled b_1(1)* 403 to 404 labelled a_1(1)* 404 to 405 labelled b_1(1)* 405 to 406 labelled a_1(1)* 406 to 407 labelled b_1(1)* 407 to 367 labelled a_1(1)* 407 to 434 labelled b_1(2)* 434 to 435 labelled a_1(2)* 435 to 436 labelled b_1(2)* 436 to 437 labelled a_1(2)* 437 to 438 labelled b_1(2)* 438 to 439 labelled a_1(2)* 438 to 434 labelled b_1(2)* 439 to 440 labelled a_1(2)* 439 to 358 labelled b_1(1)* 440 to 441 labelled b_1(2)* 441 to 442 labelled a_1(2)* 442 to 443 labelled b_1(2)* 443 to 444 labelled a_1(2)* 444 to 445 labelled b_1(2)* 445 to 367 labelled a_1(2)* 445 to 434 labelled b_1(2) 3.72/1.72 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (6) 3.72/1.72 YES 3.86/2.54 EOF popout

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all output return to SRS_Standard 2019-03-29 03.29