details

property	value
status	complete
benchmark	abaaaabaa-aaabaabaaaab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n007.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	2.31349 seconds
cpu usage	3.68053
user time	3.50891
system time	0.171622
max virtual memory	1.9010476E7
max residence set size	289820.0

stage attributes

key	value
starexec-result	YES

output

3.45/1.66 YES 3.64/2.28 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 3.64/2.28 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 3.64/2.28 3.64/2.28 3.64/2.28 Termination w.r.t. Q of the given QTRS could be proven: 3.64/2.28 3.64/2.28 (0) QTRS 3.64/2.28 (1) QTRS Reverse [EQUIVALENT, 0 ms] 3.64/2.28 (2) QTRS 3.64/2.28 (3) Strip Symbols Proof [SOUND, 0 ms] 3.64/2.28 (4) QTRS 3.64/2.28 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] 3.64/2.28 (6) YES 3.64/2.28 3.64/2.28 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (0) 3.64/2.28 Obligation: 3.64/2.28 Q restricted rewrite system: 3.64/2.28 The TRS R consists of the following rules: 3.64/2.28 3.64/2.28 a(b(a(a(a(a(b(a(a(x1))))))))) -> a(a(a(b(a(a(b(a(a(a(a(b(x1)))))))))))) 3.64/2.28 3.64/2.28 Q is empty. 3.64/2.28 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (1) QTRS Reverse (EQUIVALENT) 3.64/2.28 We applied the QTRS Reverse Processor [REVERSE]. 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (2) 3.64/2.28 Obligation: 3.64/2.28 Q restricted rewrite system: 3.64/2.28 The TRS R consists of the following rules: 3.64/2.28 3.64/2.28 a(a(b(a(a(a(a(b(a(x1))))))))) -> b(a(a(a(a(b(a(a(b(a(a(a(x1)))))))))))) 3.64/2.28 3.64/2.28 Q is empty. 3.64/2.28 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (3) Strip Symbols Proof (SOUND) 3.64/2.28 We were given the following TRS: 3.64/2.28 3.64/2.28 a(a(b(a(a(a(a(b(a(x1))))))))) -> b(a(a(a(a(b(a(a(b(a(a(a(x1)))))))))))) 3.64/2.28 3.64/2.28 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 3.64/2.28 3.64/2.28 a(a(b(a(a(a(a(b(x)))))))) -> b(a(a(a(a(b(a(a(b(a(a(x))))))))))) 3.64/2.28 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (4) 3.64/2.28 Obligation: 3.64/2.28 Q restricted rewrite system: 3.64/2.28 The TRS R consists of the following rules: 3.64/2.28 3.64/2.28 a(a(b(a(a(a(a(b(x)))))))) -> b(a(a(a(a(b(a(a(b(a(a(x))))))))))) 3.64/2.28 3.64/2.28 Q is empty. 3.64/2.28 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 3.64/2.28 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. 3.64/2.28 The following rules were used to construct the certificate: 3.64/2.28 3.64/2.28 a(a(b(a(a(a(a(b(x)))))))) -> b(a(a(a(a(b(a(a(b(a(a(x))))))))))) 3.64/2.28 3.64/2.28 The certificate found is represented by the following graph. 3.64/2.28 The certificate consists of the following enumerated nodes: 3.64/2.28 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570 3.64/2.28 3.64/2.28 Node 549 is start node and node 550 is final node. 3.64/2.28 3.64/2.28 Those nodes are connected through the following edges: 3.64/2.28 3.64/2.28 * 549 to 551 labelled b_1(0)* 550 to 550 labelled #_1(0)* 551 to 552 labelled a_1(0)* 552 to 553 labelled a_1(0)* 553 to 554 labelled a_1(0)* 554 to 555 labelled a_1(0)* 555 to 556 labelled b_1(0)* 556 to 557 labelled a_1(0)* 556 to 561 labelled b_1(1)* 557 to 558 labelled a_1(0)* 558 to 559 labelled b_1(0)* 559 to 560 labelled a_1(0)* 559 to 561 labelled b_1(1)* 560 to 550 labelled a_1(0)* 560 to 561 labelled b_1(1)* 561 to 562 labelled a_1(1)* 562 to 563 labelled a_1(1)* 563 to 564 labelled a_1(1)* 564 to 565 labelled a_1(1)* 565 to 566 labelled b_1(1)* 566 to 567 labelled a_1(1)* 566 to 561 labelled b_1(1)* 567 to 568 labelled a_1(1)* 568 to 569 labelled b_1(1)* 569 to 570 labelled a_1(1)* 569 to 561 labelled b_1(1)* 570 to 550 labelled a_1(1)* 570 to 561 labelled b_1(1) 3.64/2.28 3.64/2.28 3.64/2.28 ---------------------------------------- 3.64/2.28 3.64/2.28 (6) 3.64/2.28 YES 3.66/2.31 EOF popout

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all output return to SRS_Standard 2019-03-29 03.29