details

property	value
status	complete
benchmark	abbaaaa-aaaaabbabbaabb.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n046.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.84266 seconds
cpu usage	4.32967
user time	4.12795
system time	0.201714
max virtual memory	1.927422E7
max residence set size	408672.0

stage attributes

key	value
starexec-result	YES

output

4.15/1.77 YES 4.26/1.80 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 4.26/1.80 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 4.26/1.80 4.26/1.80 4.26/1.80 Termination w.r.t. Q of the given QTRS could be proven: 4.26/1.80 4.26/1.80 (0) QTRS 4.26/1.80 (1) QTRS Reverse [EQUIVALENT, 0 ms] 4.26/1.80 (2) QTRS 4.26/1.80 (3) Strip Symbols Proof [SOUND, 0 ms] 4.26/1.80 (4) QTRS 4.26/1.80 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] 4.26/1.80 (6) YES 4.26/1.80 4.26/1.80 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (0) 4.26/1.80 Obligation: 4.26/1.80 Q restricted rewrite system: 4.26/1.80 The TRS R consists of the following rules: 4.26/1.80 4.26/1.80 a(b(b(a(a(a(a(x1))))))) -> a(a(a(a(a(b(b(a(b(b(a(a(b(b(x1)))))))))))))) 4.26/1.80 4.26/1.80 Q is empty. 4.26/1.80 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (1) QTRS Reverse (EQUIVALENT) 4.26/1.80 We applied the QTRS Reverse Processor [REVERSE]. 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (2) 4.26/1.80 Obligation: 4.26/1.80 Q restricted rewrite system: 4.26/1.80 The TRS R consists of the following rules: 4.26/1.80 4.26/1.80 a(a(a(a(b(b(a(x1))))))) -> b(b(a(a(b(b(a(b(b(a(a(a(a(a(x1)))))))))))))) 4.26/1.80 4.26/1.80 Q is empty. 4.26/1.80 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (3) Strip Symbols Proof (SOUND) 4.26/1.80 We were given the following TRS: 4.26/1.80 4.26/1.80 a(a(a(a(b(b(a(x1))))))) -> b(b(a(a(b(b(a(b(b(a(a(a(a(a(x1)))))))))))))) 4.26/1.80 4.26/1.80 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 4.26/1.80 4.26/1.80 a(a(a(a(b(b(x)))))) -> b(b(a(a(b(b(a(b(b(a(a(a(a(x))))))))))))) 4.26/1.80 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (4) 4.26/1.80 Obligation: 4.26/1.80 Q restricted rewrite system: 4.26/1.80 The TRS R consists of the following rules: 4.26/1.80 4.26/1.80 a(a(a(a(b(b(x)))))) -> b(b(a(a(b(b(a(b(b(a(a(a(a(x))))))))))))) 4.26/1.80 4.26/1.80 Q is empty. 4.26/1.80 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 4.26/1.80 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. 4.26/1.80 The following rules were used to construct the certificate: 4.26/1.80 4.26/1.80 a(a(a(a(b(b(x)))))) -> b(b(a(a(b(b(a(b(b(a(a(a(a(x))))))))))))) 4.26/1.80 4.26/1.80 The certificate found is represented by the following graph. 4.26/1.80 The certificate consists of the following enumerated nodes: 4.26/1.80 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550 4.26/1.80 4.26/1.80 Node 525 is start node and node 526 is final node. 4.26/1.80 4.26/1.80 Those nodes are connected through the following edges: 4.26/1.80 4.26/1.80 * 525 to 527 labelled b_1(0)* 526 to 526 labelled #_1(0)* 527 to 528 labelled b_1(0)* 528 to 529 labelled a_1(0)* 529 to 530 labelled a_1(0)* 530 to 531 labelled b_1(0)* 531 to 532 labelled b_1(0)* 532 to 533 labelled a_1(0)* 533 to 534 labelled b_1(0)* 534 to 535 labelled b_1(0)* 535 to 536 labelled a_1(0)* 535 to 539 labelled b_1(1)* 536 to 537 labelled a_1(0)* 536 to 539 labelled b_1(1)* 537 to 538 labelled a_1(0)* 537 to 539 labelled b_1(1)* 538 to 526 labelled a_1(0)* 538 to 539 labelled b_1(1)* 539 to 540 labelled b_1(1)* 540 to 541 labelled a_1(1)* 541 to 542 labelled a_1(1)* 542 to 543 labelled b_1(1)* 543 to 544 labelled b_1(1)* 544 to 545 labelled a_1(1)* 545 to 546 labelled b_1(1)* 546 to 547 labelled b_1(1)* 547 to 548 labelled a_1(1)* 547 to 539 labelled b_1(1)* 548 to 549 labelled a_1(1)* 548 to 539 labelled b_1(1)* 549 to 550 labelled a_1(1)* 549 to 539 labelled b_1(1)* 550 to 526 labelled a_1(1)* 550 to 539 labelled b_1(1) 4.26/1.80 4.26/1.80 4.26/1.80 ---------------------------------------- 4.26/1.80 4.26/1.80 (6) 4.26/1.80 YES 4.30/1.84 EOF popout

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