details

property	value
status	complete
benchmark	abaaaaabaa-aaaaababaaaaab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n105.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.84987 seconds
cpu usage	4.04204
user time	3.86741
system time	0.174623
max virtual memory	1.8811124E7
max residence set size	344908.0

stage attributes

key	value
starexec-result	YES

output

3.74/1.79 YES 3.74/1.82 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 3.74/1.82 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 3.74/1.82 3.74/1.82 3.74/1.82 Termination w.r.t. Q of the given QTRS could be proven: 3.74/1.82 3.74/1.82 (0) QTRS 3.74/1.82 (1) QTRS Reverse [EQUIVALENT, 0 ms] 3.74/1.82 (2) QTRS 3.74/1.82 (3) Strip Symbols Proof [SOUND, 0 ms] 3.74/1.82 (4) QTRS 3.74/1.82 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] 3.74/1.82 (6) YES 3.74/1.82 3.74/1.82 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (0) 3.74/1.82 Obligation: 3.74/1.82 Q restricted rewrite system: 3.74/1.82 The TRS R consists of the following rules: 3.74/1.82 3.74/1.82 a(b(a(a(a(a(a(b(a(a(x1)))))))))) -> a(a(a(a(a(b(a(b(a(a(a(a(a(b(x1)))))))))))))) 3.74/1.82 3.74/1.82 Q is empty. 3.74/1.82 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (1) QTRS Reverse (EQUIVALENT) 3.74/1.82 We applied the QTRS Reverse Processor [REVERSE]. 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (2) 3.74/1.82 Obligation: 3.74/1.82 Q restricted rewrite system: 3.74/1.82 The TRS R consists of the following rules: 3.74/1.82 3.74/1.82 a(a(b(a(a(a(a(a(b(a(x1)))))))))) -> b(a(a(a(a(a(b(a(b(a(a(a(a(a(x1)))))))))))))) 3.74/1.82 3.74/1.82 Q is empty. 3.74/1.82 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (3) Strip Symbols Proof (SOUND) 3.74/1.82 We were given the following TRS: 3.74/1.82 3.74/1.82 a(a(b(a(a(a(a(a(b(a(x1)))))))))) -> b(a(a(a(a(a(b(a(b(a(a(a(a(a(x1)))))))))))))) 3.74/1.82 3.74/1.82 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 3.74/1.82 3.74/1.82 a(a(b(a(a(a(a(a(b(x))))))))) -> b(a(a(a(a(a(b(a(b(a(a(a(a(x))))))))))))) 3.74/1.82 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (4) 3.74/1.82 Obligation: 3.74/1.82 Q restricted rewrite system: 3.74/1.82 The TRS R consists of the following rules: 3.74/1.82 3.74/1.82 a(a(b(a(a(a(a(a(b(x))))))))) -> b(a(a(a(a(a(b(a(b(a(a(a(a(x))))))))))))) 3.74/1.82 3.74/1.82 Q is empty. 3.74/1.82 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 3.74/1.82 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 2. This implies Q-termination of R. 3.74/1.82 The following rules were used to construct the certificate: 3.74/1.82 3.74/1.82 a(a(b(a(a(a(a(a(b(x))))))))) -> b(a(a(a(a(a(b(a(b(a(a(a(a(x))))))))))))) 3.74/1.82 3.74/1.82 The certificate found is represented by the following graph. 3.74/1.82 The certificate consists of the following enumerated nodes: 3.74/1.82 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588 3.74/1.82 3.74/1.82 Node 539 is start node and node 540 is final node. 3.74/1.82 3.74/1.82 Those nodes are connected through the following edges: 3.74/1.82 3.74/1.82 * 539 to 541 labelled b_1(0)* 540 to 540 labelled #_1(0)* 541 to 542 labelled a_1(0)* 542 to 543 labelled a_1(0)* 543 to 544 labelled a_1(0)* 544 to 545 labelled a_1(0)* 545 to 546 labelled a_1(0)* 546 to 547 labelled b_1(0)* 547 to 548 labelled a_1(0)* 548 to 549 labelled b_1(0)* 549 to 550 labelled a_1(0)* 549 to 565 labelled b_1(1)* 550 to 551 labelled a_1(0)* 550 to 565 labelled b_1(1)* 551 to 552 labelled a_1(0)* 551 to 553 labelled b_1(1)* 552 to 540 labelled a_1(0)* 552 to 553 labelled b_1(1)* 553 to 554 labelled a_1(1)* 554 to 555 labelled a_1(1)* 555 to 556 labelled a_1(1)* 556 to 557 labelled a_1(1)* 557 to 558 labelled a_1(1)* 558 to 559 labelled b_1(1)* 559 to 560 labelled a_1(1)* 560 to 561 labelled b_1(1)* 561 to 562 labelled a_1(1)* 561 to 577 labelled b_1(2)* 562 to 563 labelled a_1(1)* 562 to 577 labelled b_1(2)* 563 to 564 labelled a_1(1)* 563 to 553 labelled b_1(1)* 564 to 540 labelled a_1(1)* 564 to 553 labelled b_1(1)* 565 to 566 labelled a_1(1)* 566 to 567 labelled a_1(1)* 567 to 568 labelled a_1(1)* 568 to 569 labelled a_1(1)* 569 to 570 labelled a_1(1)* 570 to 571 labelled b_1(1)* 571 to 572 labelled a_1(1)* 572 to 573 labelled b_1(1)* 573 to 574 labelled a_1(1)* 574 to 575 labelled a_1(1)* 574 to 577 labelled b_1(2)* 575 to 576 labelled a_1(1)* 576 to 559 labelled a_1(1)* 576 to 553 labelled b_1(1)* 577 to 578 labelled a_1(2)* 578 to 579 labelled a_1(2)* 579 to 580 labelled a_1(2)* 580 to 581 labelled a_1(2)* 581 to 582 labelled a_1(2)* 582 to 583 labelled b_1(2)* 583 to 584 labelled a_1(2)* 584 to 585 labelled b_1(2)* 585 to 586 labelled a_1(2)* 586 to 587 labelled a_1(2)* 586 to 577 labelled b_1(2)* 587 to 588 labelled a_1(2)* 588 to 559 labelled a_1(2)* 588 to 553 labelled b_1(1) 3.74/1.82 3.74/1.82 3.74/1.82 ---------------------------------------- 3.74/1.82 3.74/1.82 (6) 3.74/1.82 YES 4.02/1.84 EOF popout

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