details

property	value
status	complete
benchmark	abaaaaaaa-aaaaaaaababaab.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n160.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.75821 seconds
cpu usage	3.8292
user time	3.64869
system time	0.180507
max virtual memory	1.8877348E7
max residence set size	285952.0

stage attributes

key	value
starexec-result	YES

output

3.47/1.67 YES 3.72/1.72 proof of /export/starexec/sandbox/benchmark/theBenchmark.xml 3.72/1.72 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 3.72/1.72 3.72/1.72 3.72/1.72 Termination w.r.t. Q of the given QTRS could be proven: 3.72/1.72 3.72/1.72 (0) QTRS 3.72/1.72 (1) QTRS Reverse [EQUIVALENT, 0 ms] 3.72/1.72 (2) QTRS 3.72/1.72 (3) Strip Symbols Proof [SOUND, 0 ms] 3.72/1.72 (4) QTRS 3.72/1.72 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] 3.72/1.72 (6) YES 3.72/1.72 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (0) 3.72/1.72 Obligation: 3.72/1.72 Q restricted rewrite system: 3.72/1.72 The TRS R consists of the following rules: 3.72/1.72 3.72/1.72 a(b(a(a(a(a(a(a(a(x1))))))))) -> a(a(a(a(a(a(a(a(b(a(b(a(a(b(x1)))))))))))))) 3.72/1.72 3.72/1.72 Q is empty. 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (1) QTRS Reverse (EQUIVALENT) 3.72/1.72 We applied the QTRS Reverse Processor [REVERSE]. 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (2) 3.72/1.72 Obligation: 3.72/1.72 Q restricted rewrite system: 3.72/1.72 The TRS R consists of the following rules: 3.72/1.72 3.72/1.72 a(a(a(a(a(a(a(b(a(x1))))))))) -> b(a(a(b(a(b(a(a(a(a(a(a(a(a(x1)))))))))))))) 3.72/1.72 3.72/1.72 Q is empty. 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (3) Strip Symbols Proof (SOUND) 3.72/1.72 We were given the following TRS: 3.72/1.72 3.72/1.72 a(a(a(a(a(a(a(b(a(x1))))))))) -> b(a(a(b(a(b(a(a(a(a(a(a(a(a(x1)))))))))))))) 3.72/1.72 3.72/1.72 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 3.72/1.72 3.72/1.72 a(a(a(a(a(a(a(b(x)))))))) -> b(a(a(b(a(b(a(a(a(a(a(a(a(x))))))))))))) 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (4) 3.72/1.72 Obligation: 3.72/1.72 Q restricted rewrite system: 3.72/1.72 The TRS R consists of the following rules: 3.72/1.72 3.72/1.72 a(a(a(a(a(a(a(b(x)))))))) -> b(a(a(b(a(b(a(a(a(a(a(a(a(x))))))))))))) 3.72/1.72 3.72/1.72 Q is empty. 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 3.72/1.72 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. 3.72/1.72 The following rules were used to construct the certificate: 3.72/1.72 3.72/1.72 a(a(a(a(a(a(a(b(x)))))))) -> b(a(a(b(a(b(a(a(a(a(a(a(a(x))))))))))))) 3.72/1.72 3.72/1.72 The certificate found is represented by the following graph. 3.72/1.72 The certificate consists of the following enumerated nodes: 3.72/1.72 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422 3.72/1.72 3.72/1.72 Node 397 is start node and node 398 is final node. 3.72/1.72 3.72/1.72 Those nodes are connected through the following edges: 3.72/1.72 3.72/1.72 * 397 to 399 labelled b_1(0)* 398 to 398 labelled #_1(0)* 399 to 400 labelled a_1(0)* 400 to 401 labelled a_1(0)* 401 to 402 labelled b_1(0)* 402 to 403 labelled a_1(0)* 403 to 404 labelled b_1(0)* 404 to 405 labelled a_1(0)* 404 to 411 labelled b_1(1)* 405 to 406 labelled a_1(0)* 405 to 411 labelled b_1(1)* 406 to 407 labelled a_1(0)* 406 to 411 labelled b_1(1)* 407 to 408 labelled a_1(0)* 407 to 411 labelled b_1(1)* 408 to 409 labelled a_1(0)* 408 to 411 labelled b_1(1)* 409 to 410 labelled a_1(0)* 409 to 411 labelled b_1(1)* 410 to 398 labelled a_1(0)* 410 to 411 labelled b_1(1)* 411 to 412 labelled a_1(1)* 412 to 413 labelled a_1(1)* 413 to 414 labelled b_1(1)* 414 to 415 labelled a_1(1)* 415 to 416 labelled b_1(1)* 416 to 417 labelled a_1(1)* 416 to 411 labelled b_1(1)* 417 to 418 labelled a_1(1)* 417 to 411 labelled b_1(1)* 418 to 419 labelled a_1(1)* 418 to 411 labelled b_1(1)* 419 to 420 labelled a_1(1)* 419 to 411 labelled b_1(1)* 420 to 421 labelled a_1(1)* 420 to 411 labelled b_1(1)* 421 to 422 labelled a_1(1)* 421 to 411 labelled b_1(1)* 422 to 398 labelled a_1(1)* 422 to 411 labelled b_1(1) 3.72/1.72 3.72/1.72 3.72/1.72 ---------------------------------------- 3.72/1.72 3.72/1.72 (6) 3.72/1.72 YES 3.72/1.75 EOF popout

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all output return to SRS_Standard 2019-03-29 03.29