details

property	value
status	complete
benchmark	abbaaaaa-aaaaaabbabbabb.srs.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n055.star.cs.uiowa.edu
space	Wenzel_16

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.86227 seconds
cpu usage	4.27014
user time	4.0653
system time	0.204841
max virtual memory	1.9208684E7
max residence set size	384016.0

stage attributes

key	value
starexec-result	YES

output

4.16/1.82 YES 4.16/1.82 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 4.16/1.82 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 4.16/1.82 4.16/1.82 4.16/1.82 Termination w.r.t. Q of the given QTRS could be proven: 4.16/1.82 4.16/1.82 (0) QTRS 4.16/1.82 (1) QTRS Reverse [EQUIVALENT, 0 ms] 4.16/1.82 (2) QTRS 4.16/1.82 (3) Strip Symbols Proof [SOUND, 0 ms] 4.16/1.82 (4) QTRS 4.16/1.82 (5) RFCMatchBoundsTRSProof [EQUIVALENT, 0 ms] 4.16/1.82 (6) YES 4.16/1.82 4.16/1.82 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (0) 4.16/1.82 Obligation: 4.16/1.82 Q restricted rewrite system: 4.16/1.82 The TRS R consists of the following rules: 4.16/1.82 4.16/1.82 a(b(b(a(a(a(a(a(x1)))))))) -> a(a(a(a(a(a(b(b(a(b(b(a(b(b(x1)))))))))))))) 4.16/1.82 4.16/1.82 Q is empty. 4.16/1.82 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (1) QTRS Reverse (EQUIVALENT) 4.16/1.82 We applied the QTRS Reverse Processor [REVERSE]. 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (2) 4.16/1.82 Obligation: 4.16/1.82 Q restricted rewrite system: 4.16/1.82 The TRS R consists of the following rules: 4.16/1.82 4.16/1.82 a(a(a(a(a(b(b(a(x1)))))))) -> b(b(a(b(b(a(b(b(a(a(a(a(a(a(x1)))))))))))))) 4.16/1.82 4.16/1.82 Q is empty. 4.16/1.82 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (3) Strip Symbols Proof (SOUND) 4.16/1.82 We were given the following TRS: 4.16/1.82 4.16/1.82 a(a(a(a(a(b(b(a(x1)))))))) -> b(b(a(b(b(a(b(b(a(a(a(a(a(a(x1)))))))))))))) 4.16/1.82 4.16/1.82 By stripping symbols from the only rule of the system, we obtained the following TRS [ENDRULLIS]: 4.16/1.82 4.16/1.82 a(a(a(a(a(b(b(x))))))) -> b(b(a(b(b(a(b(b(a(a(a(a(a(x))))))))))))) 4.16/1.82 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (4) 4.16/1.82 Obligation: 4.16/1.82 Q restricted rewrite system: 4.16/1.82 The TRS R consists of the following rules: 4.16/1.82 4.16/1.82 a(a(a(a(a(b(b(x))))))) -> b(b(a(b(b(a(b(b(a(a(a(a(a(x))))))))))))) 4.16/1.82 4.16/1.82 Q is empty. 4.16/1.82 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (5) RFCMatchBoundsTRSProof (EQUIVALENT) 4.16/1.82 Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 1. This implies Q-termination of R. 4.16/1.82 The following rules were used to construct the certificate: 4.16/1.82 4.16/1.82 a(a(a(a(a(b(b(x))))))) -> b(b(a(b(b(a(b(b(a(a(a(a(a(x))))))))))))) 4.16/1.82 4.16/1.82 The certificate found is represented by the following graph. 4.16/1.82 The certificate consists of the following enumerated nodes: 4.16/1.82 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563 4.16/1.82 4.16/1.82 Node 538 is start node and node 539 is final node. 4.16/1.82 4.16/1.82 Those nodes are connected through the following edges: 4.16/1.82 4.16/1.82 * 538 to 540 labelled b_1(0)* 539 to 539 labelled #_1(0)* 540 to 541 labelled b_1(0)* 541 to 542 labelled a_1(0)* 542 to 543 labelled b_1(0)* 543 to 544 labelled b_1(0)* 544 to 545 labelled a_1(0)* 545 to 546 labelled b_1(0)* 546 to 547 labelled b_1(0)* 547 to 548 labelled a_1(0)* 547 to 552 labelled b_1(1)* 548 to 549 labelled a_1(0)* 548 to 552 labelled b_1(1)* 549 to 550 labelled a_1(0)* 549 to 552 labelled b_1(1)* 550 to 551 labelled a_1(0)* 550 to 552 labelled b_1(1)* 551 to 539 labelled a_1(0)* 551 to 552 labelled b_1(1)* 552 to 553 labelled b_1(1)* 553 to 554 labelled a_1(1)* 554 to 555 labelled b_1(1)* 555 to 556 labelled b_1(1)* 556 to 557 labelled a_1(1)* 557 to 558 labelled b_1(1)* 558 to 559 labelled b_1(1)* 559 to 560 labelled a_1(1)* 559 to 552 labelled b_1(1)* 560 to 561 labelled a_1(1)* 560 to 552 labelled b_1(1)* 561 to 562 labelled a_1(1)* 561 to 552 labelled b_1(1)* 562 to 563 labelled a_1(1)* 562 to 552 labelled b_1(1)* 563 to 539 labelled a_1(1)* 563 to 552 labelled b_1(1) 4.16/1.82 4.16/1.82 4.16/1.82 ---------------------------------------- 4.16/1.82 4.16/1.82 (6) 4.16/1.82 YES 4.16/1.86 EOF popout

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