details

property	value
status	complete
benchmark	x06.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n119.star.cs.uiowa.edu
space	Secret_07_SRS

run statistics

property	value
solver	matchbox-2019-03-17
configuration	std.sh
runtime (wallclock)	27.5867 seconds
cpu usage	106.722
user time	91.4062
system time	15.3153
max virtual memory	1.16893332E8
max residence set size	1398188.0

stage attributes

key	value
starexec-result	YES

output

102.82/26.59 YES 103.12/26.66 property Termination 103.12/26.69 has value True 104.27/26.99 for SRS ( [a, b] -> [c, b], [c, c] -> [d, b], [d] -> [c, e], [b, b] -> [f], [c, b] -> [g], [e] -> [f], [e] -> [b, b], [f, g] -> [a, c], [g, f] -> [e], [a] -> [b, c]) 104.27/26.99 reason 104.27/26.99 remap for 10 rules 104.27/27.00 property Termination 104.27/27.00 has value True 104.78/27.09 for SRS ( [0, 1] -> [2, 1], [2, 2] -> [3, 1], [3] -> [2, 4], [1, 1] -> [5], [2, 1] -> [6], [4] -> [5], [4] -> [1, 1], [5, 6] -> [0, 2], [6, 5] -> [4], [0] -> [1, 2]) 104.78/27.09 reason 104.78/27.09 DP transform 104.78/27.09 property Termination 104.78/27.09 has value True 104.78/27.10 for SRS ( [0, 1] ->= [2, 1], [2, 2] ->= [3, 1], [3] ->= [2, 4], [1, 1] ->= [5], [2, 1] ->= [6], [4] ->= [5], [4] ->= [1, 1], [5, 6] ->= [0, 2], [6, 5] ->= [4], [0] ->= [1, 2], [0#, 1] |-> [2#, 1], [2#, 2] |-> [3#, 1], [2#, 2] |-> [1#], [3#] |-> [2#, 4], [3#] |-> [4#], [1#, 1] |-> [5#], [2#, 1] |-> [6#], [4#] |-> [5#], [4#] |-> [1#, 1], [4#] |-> [1#], [5#, 6] |-> [0#, 2], [5#, 6] |-> [2#], [6#, 5] |-> [4#], [0#] |-> [1#, 2], [0#] |-> [2#]) 104.78/27.10 reason 104.78/27.10 remap for 25 rules 104.78/27.10 property Termination 104.78/27.10 has value True 104.78/27.10 for SRS ( [0, 1] ->= [2, 1], [2, 2] ->= [3, 1], [3] ->= [2, 4], [1, 1] ->= [5], [2, 1] ->= [6], [4] ->= [5], [4] ->= [1, 1], [5, 6] ->= [0, 2], [6, 5] ->= [4], [0] ->= [1, 2], [7, 1] |-> [8, 1], [8, 2] |-> [9, 1], [8, 2] |-> [10], [9] |-> [8, 4], [9] |-> [11], [10, 1] |-> [12], [8, 1] |-> [13], [11] |-> [12], [11] |-> [10, 1], [11] |-> [10], [12, 6] |-> [7, 2], [12, 6] |-> [8], [13, 5] |-> [11], [7] |-> [10, 2], [7] |-> [8]) 104.78/27.10 reason 104.78/27.10 EDG has 1 SCCs 104.78/27.10 property Termination 104.78/27.10 has value True 104.78/27.14 for SRS ( [7, 1] |-> [8, 1], [8, 1] |-> [13], [13, 5] |-> [11], [11] |-> [10], [10, 1] |-> [12], [12, 6] |-> [8], [8, 2] |-> [10], [8, 2] |-> [9, 1], [9] |-> [11], [11] |-> [10, 1], [11] |-> [12], [12, 6] |-> [7, 2], [7] |-> [8], [7] |-> [10, 2], [9] |-> [8, 4], [0, 1] ->= [2, 1], [2, 2] ->= [3, 1], [3] ->= [2, 4], [1, 1] ->= [5], [2, 1] ->= [6], [4] ->= [5], [4] ->= [1, 1], [5, 6] ->= [0, 2], [6, 5] ->= [4], [0] ->= [1, 2]) 104.78/27.14 reason 104.78/27.14 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = True} 104.78/27.14 interpretation 104.78/27.14 0 / 2A 2A \ 104.78/27.14 \ 0A 0A / 104.78/27.14 1 / 0A 2A \ 104.78/27.14 \ -2A 0A / 104.78/27.14 2 / 0A 2A \ 104.78/27.14 \ 0A 0A / 104.78/27.14 3 / 0A 2A \ 104.78/27.14 \ 0A 2A / 104.78/27.14 4 / 0A 2A \ 104.78/27.14 \ -2A 0A / 104.78/27.14 5 / 0A 2A \ 104.78/27.14 \ -2A 0A / 104.78/27.14 6 / 0A 2A \ 104.78/27.14 \ 0A 2A / 104.78/27.14 7 / 7A 9A \ 104.78/27.14 \ 7A 9A / 104.78/27.14 8 / 7A 9A \ 104.78/27.14 \ 7A 9A / 104.78/27.14 9 / 7A 9A \ 104.78/27.14 \ 7A 9A / 104.78/27.14 10 / 7A 7A \ 104.78/27.14 \ 7A 7A / 104.78/27.14 11 / 7A 9A \ 104.78/27.14 \ 7A 9A / 104.78/27.14 12 / 7A 9A \ 104.78/27.14 \ 7A 9A / 104.78/27.14 13 / 7A 9A \ 104.78/27.14 \ 7A 9A / 104.78/27.14 [7, 1] |-> [8, 1] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [8, 1] |-> [13] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [13, 5] |-> [11] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [11] |-> [10] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 7A \ True False 104.78/27.14 \ 7A 9A / \ 7A 7A / 104.78/27.14 [10, 1] |-> [12] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [12, 6] |-> [8] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 9A 11A \ / 7A 9A \ True True 104.78/27.14 \ 9A 11A / \ 7A 9A / 104.78/27.14 [8, 2] |-> [10] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 9A 9A \ / 7A 7A \ True True 104.78/27.14 \ 9A 9A / \ 7A 7A / 104.78/27.14 [8, 2] |-> [9, 1] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 9A 9A \ / 7A 9A \ True False 104.78/27.14 \ 9A 9A / \ 7A 9A / 104.78/27.14 [9] |-> [11] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [11] |-> [10, 1] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [11] |-> [12] 104.78/27.14 lhs rhs ge gt 104.78/27.14 / 7A 9A \ / 7A 9A \ True False 104.78/27.14 \ 7A 9A / \ 7A 9A / 104.78/27.14 [12, 6] |-> [7, 2] popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to SRS_Standard 2019-03-29 03.29