details

property	value
status	complete
benchmark	x01.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n172.star.cs.uiowa.edu
space	Secret_07_SRS

run statistics

property	value
solver	matchbox-2019-03-17
configuration	std.sh
runtime (wallclock)	11.911 seconds
cpu usage	46.6642
user time	39.2463
system time	7.41783
max virtual memory	1.16752008E8
max residence set size	1323732.0

stage attributes

key	value
starexec-result	YES

output

45.07/11.43 YES 45.24/11.43 property Termination 45.24/11.44 has value True 45.28/11.45 for SRS ( [a] -> [b, b], [c, b] -> [d], [e, b] -> [c, c], [d, b] -> [b, f], [f] -> [a, e], [c] -> [], [a, a] -> [f]) 45.28/11.45 reason 45.28/11.45 remap for 7 rules 45.28/11.45 property Termination 45.28/11.45 has value True 45.28/11.45 for SRS ( [0] -> [1, 1], [2, 1] -> [3], [4, 1] -> [2, 2], [3, 1] -> [1, 5], [5] -> [0, 4], [2] -> [], [0, 0] -> [5]) 45.28/11.45 reason 45.28/11.46 DP transform 45.28/11.46 property Termination 45.28/11.46 has value True 45.28/11.50 for SRS ( [0] ->= [1, 1], [2, 1] ->= [3], [4, 1] ->= [2, 2], [3, 1] ->= [1, 5], [5] ->= [0, 4], [2] ->= [], [0, 0] ->= [5], [2#, 1] |-> [3#], [4#, 1] |-> [2#, 2], [4#, 1] |-> [2#], [3#, 1] |-> [5#], [5#] |-> [0#, 4], [5#] |-> [4#], [0#, 0] |-> [5#]) 45.28/11.50 reason 45.28/11.50 remap for 14 rules 45.28/11.50 property Termination 45.28/11.50 has value True 45.28/11.50 for SRS ( [0] ->= [1, 1], [2, 1] ->= [3], [4, 1] ->= [2, 2], [3, 1] ->= [1, 5], [5] ->= [0, 4], [2] ->= [], [0, 0] ->= [5], [6, 1] |-> [7], [8, 1] |-> [6, 2], [8, 1] |-> [6], [7, 1] |-> [9], [9] |-> [10, 4], [9] |-> [8], [10, 0] |-> [9]) 45.28/11.50 reason 45.28/11.50 EDG has 1 SCCs 45.28/11.50 property Termination 45.28/11.50 has value True 45.28/11.50 for SRS ( [6, 1] |-> [7], [7, 1] |-> [9], [9] |-> [8], [8, 1] |-> [6], [8, 1] |-> [6, 2], [9] |-> [10, 4], [10, 0] |-> [9], [0] ->= [1, 1], [2, 1] ->= [3], [4, 1] ->= [2, 2], [3, 1] ->= [1, 5], [5] ->= [0, 4], [2] ->= [], [0, 0] ->= [5]) 45.28/11.50 reason 45.28/11.50 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 3, solver = Minisatapi, verbose = False, tracing = True} 45.28/11.50 interpretation 45.28/11.50 0 / 3A 3A 6A \ 45.28/11.50 | 3A 3A 3A | 45.28/11.50 \ 0A 3A 3A / 45.28/11.50 1 / 0A 3A 3A \ 45.28/11.50 | 0A 0A 3A | 45.28/11.50 \ 0A 0A 0A / 45.28/11.50 2 / 0A 3A 3A \ 45.28/11.50 | -3A 0A 0A | 45.28/11.50 \ -3A 0A 0A / 45.28/11.50 3 / 3A 3A 6A \ 45.28/11.50 | 0A 0A 3A | 45.28/11.50 \ 0A 0A 3A / 45.28/11.50 4 / 0A 0A 0A \ 45.28/11.50 | -3A -3A -3A | 45.28/11.50 \ -3A -3A -3A / 45.28/11.50 5 / 3A 3A 3A \ 45.28/11.50 | 3A 3A 3A | 45.28/11.50 \ 0A 0A 0A / 45.28/11.50 6 / 21A 21A 21A \ 45.28/11.50 | 21A 21A 21A | 45.28/11.50 \ 21A 21A 21A / 45.28/11.50 7 / 21A 24A 24A \ 45.28/11.50 | 21A 24A 24A | 45.28/11.50 \ 21A 24A 24A / 45.28/11.50 8 / 21A 24A 24A \ 45.28/11.50 | 21A 24A 24A | 45.28/11.50 \ 21A 24A 24A / 45.28/11.50 9 / 24A 24A 24A \ 45.28/11.50 | 24A 24A 24A | 45.28/11.50 \ 24A 24A 24A / 45.28/11.50 10 / 21A 21A 24A \ 45.28/11.50 | 21A 21A 24A | 45.28/11.50 \ 21A 21A 24A / 45.28/11.50 [6, 1] |-> [7] 45.28/11.50 lhs rhs ge gt 45.28/11.50 / 21A 24A 24A \ / 21A 24A 24A \ True False 45.28/11.50 | 21A 24A 24A | | 21A 24A 24A | 45.28/11.50 \ 21A 24A 24A / \ 21A 24A 24A / 45.28/11.50 [7, 1] |-> [9] 45.28/11.50 lhs rhs ge gt 45.28/11.50 / 24A 24A 27A \ / 24A 24A 24A \ True False 45.28/11.50 | 24A 24A 27A | | 24A 24A 24A | 45.28/11.50 \ 24A 24A 27A / \ 24A 24A 24A / 45.28/11.50 [9] |-> [8] 45.28/11.50 lhs rhs ge gt 45.28/11.50 / 24A 24A 24A \ / 21A 24A 24A \ True False 45.28/11.50 | 24A 24A 24A | | 21A 24A 24A | 45.28/11.50 \ 24A 24A 24A / \ 21A 24A 24A / 45.28/11.50 [8, 1] |-> [6] 45.28/11.50 lhs rhs ge gt 45.28/11.50 / 24A 24A 27A \ / 21A 21A 21A \ True True 45.28/11.50 | 24A 24A 27A | | 21A 21A 21A | 45.28/11.50 \ 24A 24A 27A / \ 21A 21A 21A / 45.28/11.50 [8, 1] |-> [6, 2] 45.28/11.50 lhs rhs ge gt 45.28/11.50 / 24A 24A 27A \ / 21A 24A 24A \ True False 45.28/11.50 | 24A 24A 27A | | 21A 24A 24A | 45.28/11.50 \ 24A 24A 27A / \ 21A 24A 24A / 45.28/11.50 [9] |-> [10, 4] 45.28/11.50 lhs rhs ge gt 45.28/11.50 / 24A 24A 24A \ / 21A 21A 21A \ True True 45.74/11.57 | 24A 24A 24A | | 21A 21A 21A | 45.74/11.57 \ 24A 24A 24A / \ 21A 21A 21A / 45.74/11.57 [10, 0] |-> [9] 45.74/11.57 lhs rhs ge gt 45.74/11.57 / 24A 27A 27A \ / 24A 24A 24A \ True False 45.74/11.57 | 24A 27A 27A | | 24A 24A 24A | 45.74/11.57 \ 24A 27A 27A / \ 24A 24A 24A / 45.74/11.57 [0] ->= [1, 1] 45.74/11.57 lhs rhs ge gt 45.74/11.57 / 3A 3A 6A \ / 3A 3A 6A \ True False 45.74/11.57 | 3A 3A 3A | | 3A 3A 3A | 45.74/11.57 \ 0A 3A 3A / \ 0A 3A 3A / popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to SRS_Standard 2019-03-29 03.29