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SRS_Standard 2019-03-29 03.29 pair #432294158
details
property
value
status
complete
benchmark
sym-4.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n134.star.cs.uiowa.edu
space
Waldmann_06_SRS
run statistics
property
value
solver
matchbox-2019-03-17
configuration
std.sh
runtime (wallclock)
10.7411 seconds
cpu usage
42.0951
user time
35.7496
system time
6.34554
max virtual memory
1.1688488E8
max residence set size
952644.0
stage attributes
key
value
starexec-result
YES
output
41.51/10.59 YES 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [b, b] -> [c, c, c, c], [c] -> [], [b, c, b] -> [b, b, b]) 41.51/10.59 reason 41.51/10.59 remap for 3 rules 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [0, 0] -> [1, 1, 1, 1], [1] -> [], [0, 1, 0] -> [0, 0, 0]) 41.51/10.59 reason 41.51/10.59 reverse each lhs and rhs 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [0, 0] -> [1, 1, 1, 1], [1] -> [], [0, 1, 0] -> [0, 0, 0]) 41.51/10.59 reason 41.51/10.59 DP transform 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [0, 0] ->= [1, 1, 1, 1], [1] ->= [], [0, 1, 0] ->= [0, 0, 0], [0#, 0] |-> [1#, 1, 1, 1], [0#, 0] |-> [1#, 1, 1], [0#, 0] |-> [1#, 1], [0#, 0] |-> [1#], [0#, 1, 0] |-> [0#, 0, 0], [0#, 1, 0] |-> [0#, 0]) 41.51/10.59 reason 41.51/10.59 remap for 9 rules 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [0, 0] ->= [1, 1, 1, 1], [1] ->= [], [0, 1, 0] ->= [0, 0, 0], [2, 0] |-> [3, 1, 1, 1], [2, 0] |-> [3, 1, 1], [2, 0] |-> [3, 1], [2, 0] |-> [3], [2, 1, 0] |-> [2, 0, 0], [2, 1, 0] |-> [2, 0]) 41.51/10.59 reason 41.51/10.59 weights 41.51/10.59 Map [(2, 4/1)] 41.51/10.59 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [0, 0] ->= [1, 1, 1, 1], [1] ->= [], [0, 1, 0] ->= [0, 0, 0], [2, 1, 0] |-> [2, 0, 0], [2, 1, 0] |-> [2, 0]) 41.51/10.59 reason 41.51/10.59 EDG has 1 SCCs 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [2, 1, 0] |-> [2, 0, 0], [2, 1, 0] |-> [2, 0], [0, 0] ->= [1, 1, 1, 1], [1] ->= [], [0, 1, 0] ->= [0, 0, 0]) 41.51/10.59 reason 41.51/10.59 Matrix { monotone = Weak, domain = Arctic, bits = 4, dim = 2, solver = Minisatapi, verbose = False, tracing = True} 41.51/10.59 interpretation 41.51/10.59 0 / 2A 2A \ 41.51/10.59 \ 2A 2A / 41.51/10.59 1 / 0A 2A \ 41.51/10.59 \ -2A 0A / 41.51/10.59 2 / 26A 26A \ 41.51/10.59 \ 26A 26A / 41.51/10.59 [2, 1, 0] |-> [2, 0, 0] 41.51/10.59 lhs rhs ge gt 41.51/10.59 / 30A 30A \ / 30A 30A \ True False 41.51/10.59 \ 30A 30A / \ 30A 30A / 41.51/10.59 [2, 1, 0] |-> [2, 0] 41.51/10.59 lhs rhs ge gt 41.51/10.59 / 30A 30A \ / 28A 28A \ True True 41.51/10.59 \ 30A 30A / \ 28A 28A / 41.51/10.59 [0, 0] ->= [1, 1, 1, 1] 41.51/10.59 lhs rhs ge gt 41.51/10.59 / 4A 4A \ / 0A 2A \ True True 41.51/10.59 \ 4A 4A / \ -2A 0A / 41.51/10.59 [1] ->= [] 41.51/10.59 lhs rhs ge gt 41.51/10.59 / 0A 2A \ / 0A - \ True False 41.51/10.59 \ -2A 0A / \ - 0A / 41.51/10.59 [0, 1, 0] ->= [0, 0, 0] 41.51/10.59 lhs rhs ge gt 41.51/10.59 / 6A 6A \ / 6A 6A \ True False 41.51/10.59 \ 6A 6A / \ 6A 6A / 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [2, 1, 0] |-> [2, 0, 0], [0, 0] ->= [1, 1, 1, 1], [1] ->= [], [0, 1, 0] ->= [0, 0, 0]) 41.51/10.59 reason 41.51/10.59 EDG has 1 SCCs 41.51/10.59 property Termination 41.51/10.59 has value True 41.51/10.59 for SRS ( [2, 1, 0] |-> [2, 0, 0], [0, 0] ->= [1, 1, 1, 1], [1] ->= [], [0, 1, 0] ->= [0, 0, 0]) 41.51/10.60 reason 41.51/10.60 Matrix { monotone = Weak, domain = Arctic, bits = 3, dim = 4, solver = Minisatapi, verbose = False, tracing = False} 41.51/10.60 interpretation 41.51/10.60 0 Wk / 1A 1A 1A 0A \ 41.51/10.60 | 3A - 1A - | 41.51/10.60 | - 2A 0A 0A | 41.51/10.60 \ - - - 0A / 41.51/10.60 1 Wk / 0A - - - \ 41.51/10.60 | - 0A - - | 41.51/10.60 | 5A 1A 0A - | 41.51/10.60 \ - - - 0A / 41.51/10.60 2 Wk / - 0A 1A 0A \ 41.51/10.60 | - - - - | 41.51/10.60 | - - - - | 41.51/10.60 \ - - - 0A / 41.51/10.60 [2, 1, 0] |-> [2, 0, 0] 41.51/10.60 lhs rhs ge gt 41.51/10.60 Wk / 7A 7A 7A 6A \ Wk / 6A 4A 4A 3A \ True True 41.51/10.60 | - - - - | | - - - - | 41.51/10.60 | - - - - | | - - - - | 41.51/10.60 \ - - - 0A / \ - - - 0A / 41.51/10.60 [0, 0] ->= [1, 1, 1, 1] 41.51/10.60 lhs rhs ge gt 41.51/10.60 Wk / 4A 3A 2A 1A \ Wk / 0A - - - \ True False 41.51/10.60 | 4A 4A 4A 3A | | - 0A - - | 41.51/10.60 | 5A 2A 3A 0A | | 5A 1A 0A - | 41.51/10.60 \ - - - 0A / \ - - - 0A /
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