details

property	value
status	complete
benchmark	random-123.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n039.star.cs.uiowa.edu
space	Waldmann_19

run statistics

property	value
solver	matchbox-2019-03-17
configuration	std.sh
runtime (wallclock)	12.14 seconds
cpu usage	47.9086
user time	42.1053
system time	5.80334
max virtual memory	1.16819596E8
max residence set size	1115720.0

stage attributes

key	value
starexec-result	NO

output

21.29/5.42 NO 21.29/5.42 property Termination 21.29/5.42 has value False 21.41/5.43 for SRS ( [b, a, b, b] -> [b, b, b, b], [b, a, a, b] -> [a, b, a, a], [a, a, a, a] -> [b, b, b, a]) 21.41/5.43 reason 21.43/5.43 remap for 3 rules 21.43/5.43 property Termination 21.43/5.43 has value False 21.43/5.45 for SRS ( [0, 1, 0, 0] -> [0, 0, 0, 0], [0, 1, 1, 0] -> [1, 0, 1, 1], [1, 1, 1, 1] -> [0, 0, 0, 1]) 21.43/5.45 reason 21.43/5.45 looping SRS derivation 21.43/5.45 Closure source : abbaaaaaaaaaab 21.43/5.45 target : abbaaaaaaaaaab 21.43/5.45 steps : 36 21.43/5.45 strict : True 21.43/5.45 last_rule_app_source : 0 21.43/5.45 last_rule_app_target : 6 21.43/5.45 reason : Overlap (Inside 6) 21.43/5.45 Overlap (Inside 8) 21.43/5.45 Overlap (Inside 10) 21.43/5.45 Overlap (Inside 3) 21.43/5.45 Overlap (Inside 7) 21.43/5.45 Overlap (Inside 5) 21.43/5.46 Overlap (Inside 9) 21.43/5.46 Overlap (Inside 8) 21.43/5.46 Overlap (Inside 7) 21.43/5.46 Overlap (Right 3) 21.43/5.46 Overlap (Inside 6) 21.43/5.46 Overlap (Inside 8) 21.43/5.47 Overlap (Inside 2) 21.43/5.47 Overlap (Inside 1) 21.43/5.47 Overlap (Inside 4) 21.43/5.47 Overlap (Inside 7) 21.43/5.47 Overlap (Inside 6) 21.43/5.47 Overlap (Inside 5) 21.43/5.47 Overlap (Inside 4) 21.43/5.47 Overlap (Inside 3) 21.43/5.47 Overlap (Inside 6) 21.43/5.47 Overlap (Inside 9) 21.43/5.47 Overlap (Inside 7) 21.43/5.47 Overlap (Right 3) 21.43/5.48 Overlap (Inside 2) 21.43/5.48 Overlap (Inside 5) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Inside 0) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Overlap (Right 3) 21.43/5.48 Rule 1 21.43/5.48 Rule 1 21.43/5.48 Rule 1 21.43/5.48 Rule 1 21.43/5.48 Rule 2 21.43/5.48 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 2 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 2 21.43/5.49 Rule 0 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 2 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 1 21.43/5.49 Rule 2 21.43/5.49 Rule 1 21.43/5.50 Rule 1 21.43/5.50 Rule 1 21.43/5.50 Rule 2 21.43/5.50 Rule 1 21.43/5.50 Rule 0 21.43/5.50 Rule 2 21.43/5.50 Rule 0 21.43/5.50 Rule 0 21.43/5.50 21.43/5.50 21.43/5.50 ************************************************** 21.43/5.50 summary 21.43/5.50 ************************************************** 21.43/5.50 SRS with 3 rules on 2 letters Remap { tracing = False} 21.73/5.51 SRS with 3 rules on 2 letters looping SRS derivation 21.73/5.51 Closure source : abbaaaaaaaaaab 21.73/5.51 target : abbaaaaaaaaaab 21.73/5.51 steps : 36 21.73/5.51 strict : True 21.73/5.51 last_rule_app_source : 0 popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS_Standard 2019-03-29 03.29