Runtime_Complexity_Full_Rewriting 2019-04-01 06.11 pair #433308165

details

property	value
status	complete
benchmark	LengthOfFiniteLists_complete-noand_FR.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n119.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	AProVE
configuration	complexity
runtime (wallclock)	3.65771 seconds
cpu usage	11.1086
user time	10.4491
system time	0.659491
max virtual memory	1.8277336E7
max residence set size	2271800.0

stage attributes

key	value
starexec-result	WORST_CASE(NON_POLY, ?)

output

10.72/3.59	WORST_CASE(NON_POLY, ?)
10.72/3.60	proof of /export/starexec/sandbox/benchmark/theBenchmark.xml
10.72/3.60	# AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty
10.72/3.60	
10.72/3.60	
10.72/3.60	The Runtime Complexity (full) of the given CpxTRS could be proven to be BOUNDS(EXP, INF).
10.72/3.60	
10.72/3.60	(0) CpxTRS
10.72/3.60	(1) RelTrsToDecreasingLoopProblemProof [LOWER BOUND(ID), 0 ms]
10.72/3.60	(2) TRS for Loop Detection
10.72/3.60	(3) DecreasingLoopProof [LOWER BOUND(ID), 0 ms]
10.72/3.60	(4) BEST
10.72/3.60	    (5) proven lower bound
10.72/3.60	        (6) LowerBoundPropagationProof [FINISHED, 0 ms]
10.72/3.60	        (7) BOUNDS(n^1, INF)
10.72/3.60	    (8) TRS for Loop Detection
10.72/3.60	        (9) DecreasingLoopProof [FINISHED, 1585 ms]
10.72/3.60	        (10) BOUNDS(EXP, INF)
10.72/3.60	
10.72/3.60	
10.72/3.60	----------------------------------------
10.72/3.60	
10.72/3.60	(0)
10.72/3.60	Obligation:
10.72/3.60	The Runtime Complexity (full) of the given CpxTRS could be proven to be BOUNDS(EXP, INF).
10.72/3.60	
10.72/3.60	
10.72/3.60	The TRS R consists of the following rules:
10.72/3.60	
10.72/3.60	   zeros -> cons(0, n__zeros)
10.72/3.60	   U11(tt, V1) -> U12(isNatIListKind(activate(V1)), activate(V1))
10.72/3.60	   U12(tt, V1) -> U13(isNatList(activate(V1)))
10.72/3.60	   U13(tt) -> tt
10.72/3.60	   U21(tt, V1) -> U22(isNatKind(activate(V1)), activate(V1))
10.72/3.60	   U22(tt, V1) -> U23(isNat(activate(V1)))
10.72/3.60	   U23(tt) -> tt
10.72/3.60	   U31(tt, V) -> U32(isNatIListKind(activate(V)), activate(V))
10.72/3.60	   U32(tt, V) -> U33(isNatList(activate(V)))
10.72/3.60	   U33(tt) -> tt
10.72/3.60	   U41(tt, V1, V2) -> U42(isNatKind(activate(V1)), activate(V1), activate(V2))
10.72/3.60	   U42(tt, V1, V2) -> U43(isNatIListKind(activate(V2)), activate(V1), activate(V2))
10.72/3.60	   U43(tt, V1, V2) -> U44(isNatIListKind(activate(V2)), activate(V1), activate(V2))
10.72/3.60	   U44(tt, V1, V2) -> U45(isNat(activate(V1)), activate(V2))
10.72/3.60	   U45(tt, V2) -> U46(isNatIList(activate(V2)))
10.72/3.60	   U46(tt) -> tt
10.72/3.60	   U51(tt, V2) -> U52(isNatIListKind(activate(V2)))
10.72/3.60	   U52(tt) -> tt
10.72/3.60	   U61(tt) -> tt
10.72/3.60	   U71(tt) -> tt
10.72/3.60	   U81(tt, V1, V2) -> U82(isNatKind(activate(V1)), activate(V1), activate(V2))
10.72/3.60	   U82(tt, V1, V2) -> U83(isNatIListKind(activate(V2)), activate(V1), activate(V2))
10.72/3.60	   U83(tt, V1, V2) -> U84(isNatIListKind(activate(V2)), activate(V1), activate(V2))
10.72/3.60	   U84(tt, V1, V2) -> U85(isNat(activate(V1)), activate(V2))
10.72/3.60	   U85(tt, V2) -> U86(isNatList(activate(V2)))
10.72/3.60	   U86(tt) -> tt
10.72/3.60	   U91(tt, L, N) -> U92(isNatIListKind(activate(L)), activate(L), activate(N))
10.72/3.60	   U92(tt, L, N) -> U93(isNat(activate(N)), activate(L), activate(N))
10.72/3.60	   U93(tt, L, N) -> U94(isNatKind(activate(N)), activate(L))
10.72/3.60	   U94(tt, L) -> s(length(activate(L)))
10.72/3.60	   isNat(n__0) -> tt
10.72/3.60	   isNat(n__length(V1)) -> U11(isNatIListKind(activate(V1)), activate(V1))
10.72/3.60	   isNat(n__s(V1)) -> U21(isNatKind(activate(V1)), activate(V1))
10.72/3.60	   isNatIList(V) -> U31(isNatIListKind(activate(V)), activate(V))
10.72/3.60	   isNatIList(n__zeros) -> tt
10.72/3.60	   isNatIList(n__cons(V1, V2)) -> U41(isNatKind(activate(V1)), activate(V1), activate(V2))
10.72/3.60	   isNatIListKind(n__nil) -> tt
10.72/3.60	   isNatIListKind(n__zeros) -> tt
10.72/3.60	   isNatIListKind(n__cons(V1, V2)) -> U51(isNatKind(activate(V1)), activate(V2))
10.72/3.60	   isNatKind(n__0) -> tt
10.72/3.60	   isNatKind(n__length(V1)) -> U61(isNatIListKind(activate(V1)))
10.72/3.60	   isNatKind(n__s(V1)) -> U71(isNatKind(activate(V1)))
10.72/3.60	   isNatList(n__nil) -> tt
10.72/3.60	   isNatList(n__cons(V1, V2)) -> U81(isNatKind(activate(V1)), activate(V1), activate(V2))
10.72/3.60	   length(nil) -> 0
10.72/3.60	   length(cons(N, L)) -> U91(isNatList(activate(L)), activate(L), N)
10.72/3.60	   zeros -> n__zeros
10.72/3.60	   0 -> n__0
10.72/3.60	   length(X) -> n__length(X)
10.72/3.60	   s(X) -> n__s(X)
10.72/3.60	   cons(X1, X2) -> n__cons(X1, X2)
10.72/3.60	   nil -> n__nil
10.72/3.60	   activate(n__zeros) -> zeros
10.72/3.60	   activate(n__0) -> 0
10.72/3.60	   activate(n__length(X)) -> length(activate(X))
10.72/3.60	   activate(n__s(X)) -> s(activate(X))
10.72/3.60	   activate(n__cons(X1, X2)) -> cons(activate(X1), X2)
10.72/3.60	   activate(n__nil) -> nil
10.72/3.60	   activate(X) -> X
10.72/3.60	
10.72/3.60	S is empty.
10.72/3.60	Rewrite Strategy: FULL
10.72/3.60	----------------------------------------
10.72/3.60	
10.72/3.60	(1) RelTrsToDecreasingLoopProblemProof (LOWER BOUND(ID))
10.72/3.60	Transformed a relative TRS into a decreasing-loop problem.
10.72/3.60	----------------------------------------
10.72/3.60	
10.72/3.60	(2)
10.72/3.60	Obligation:
10.72/3.60	Analyzing the following TRS for decreasing loops:

popout

output may be truncated. 'popout' for the full output.

job log

popout

actions all output return to Runtime_Complexity_Full_Rewriting 2019-04-01 06.11