details

property	value
status	complete
benchmark	t014.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n182.star.cs.uiowa.edu
space	HirokawaMiddeldorp_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.0523331 seconds
cpu usage	0.040905
user time	0.021595
system time	0.01931
max virtual memory	113188.0
max residence set size	5728.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S x:S y:S) (RULES -(0,s(y:S)) -> 0 -(s(x:S),s(y:S)) -> -(x:S,y:S) -(x:S,0) -> x:S div(0,y:S) -> 0 div(s(x:S),s(y:S)) -> if(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) div(x:S,0) -> 0 if(ffalse,x:S,y:S) -> y:S if(ttrue,x:S,y:S) -> x:S lt(0,s(y:S)) -> ttrue lt(s(x:S),s(y:S)) -> lt(x:S,y:S) lt(x:S,0) -> ffalse ) Problem 1: Innermost Equivalent Processor: -> Rules: -(0,s(y:S)) -> 0 -(s(x:S),s(y:S)) -> -(x:S,y:S) -(x:S,0) -> x:S div(0,y:S) -> 0 div(s(x:S),s(y:S)) -> if(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) div(x:S,0) -> 0 if(ffalse,x:S,y:S) -> y:S if(ttrue,x:S,y:S) -> x:S lt(0,s(y:S)) -> ttrue lt(s(x:S),s(y:S)) -> lt(x:S,y:S) lt(x:S,0) -> ffalse -> The term rewriting system is non-overlaping or locally confluent overlay system. Therefore, innermost termination implies termination. Problem 1: Dependency Pairs Processor: -> Pairs: -#(s(x:S),s(y:S)) -> -#(x:S,y:S) DIV(s(x:S),s(y:S)) -> -#(x:S,y:S) DIV(s(x:S),s(y:S)) -> DIV(-(x:S,y:S),s(y:S)) DIV(s(x:S),s(y:S)) -> IF(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) DIV(s(x:S),s(y:S)) -> LT(x:S,y:S) LT(s(x:S),s(y:S)) -> LT(x:S,y:S) -> Rules: -(0,s(y:S)) -> 0 -(s(x:S),s(y:S)) -> -(x:S,y:S) -(x:S,0) -> x:S div(0,y:S) -> 0 div(s(x:S),s(y:S)) -> if(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) div(x:S,0) -> 0 if(ffalse,x:S,y:S) -> y:S if(ttrue,x:S,y:S) -> x:S lt(0,s(y:S)) -> ttrue lt(s(x:S),s(y:S)) -> lt(x:S,y:S) lt(x:S,0) -> ffalse Problem 1: SCC Processor: -> Pairs: -#(s(x:S),s(y:S)) -> -#(x:S,y:S) DIV(s(x:S),s(y:S)) -> -#(x:S,y:S) DIV(s(x:S),s(y:S)) -> DIV(-(x:S,y:S),s(y:S)) DIV(s(x:S),s(y:S)) -> IF(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) DIV(s(x:S),s(y:S)) -> LT(x:S,y:S) LT(s(x:S),s(y:S)) -> LT(x:S,y:S) -> Rules: -(0,s(y:S)) -> 0 -(s(x:S),s(y:S)) -> -(x:S,y:S) -(x:S,0) -> x:S div(0,y:S) -> 0 div(s(x:S),s(y:S)) -> if(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) div(x:S,0) -> 0 if(ffalse,x:S,y:S) -> y:S if(ttrue,x:S,y:S) -> x:S lt(0,s(y:S)) -> ttrue lt(s(x:S),s(y:S)) -> lt(x:S,y:S) lt(x:S,0) -> ffalse ->Strongly Connected Components: ->->Cycle: ->->-> Pairs: LT(s(x:S),s(y:S)) -> LT(x:S,y:S) ->->-> Rules: -(0,s(y:S)) -> 0 -(s(x:S),s(y:S)) -> -(x:S,y:S) -(x:S,0) -> x:S div(0,y:S) -> 0 div(s(x:S),s(y:S)) -> if(lt(x:S,y:S),0,s(div(-(x:S,y:S),s(y:S)))) div(x:S,0) -> 0 if(ffalse,x:S,y:S) -> y:S if(ttrue,x:S,y:S) -> x:S lt(0,s(y:S)) -> ttrue lt(s(x:S),s(y:S)) -> lt(x:S,y:S) lt(x:S,0) -> ffalse ->->Cycle: ->->-> Pairs: popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Standard