details

property	value
status	complete
benchmark	PEANO_nokinds_Z.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n189.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	ttt2-1.20
configuration	ttt2
runtime (wallclock)	5.90636 seconds
cpu usage	20.0402
user time	17.0109
system time	3.02933
max virtual memory	6027188.0
max residence set size	149844.0

stage attributes

key	value
starexec-result	YES

output

YES Problem: U11(tt(),N) -> activate(N) U21(tt(),M,N) -> s(plus(activate(N),activate(M))) and(tt(),X) -> activate(X) isNat(n__0()) -> tt() isNat(n__plus(V1,V2)) -> and(isNat(activate(V1)),n__isNat(activate(V2))) isNat(n__s(V1)) -> isNat(activate(V1)) plus(N,0()) -> U11(isNat(N),N) plus(N,s(M)) -> U21(and(isNat(M),n__isNat(N)),M,N) 0() -> n__0() plus(X1,X2) -> n__plus(X1,X2) isNat(X) -> n__isNat(X) s(X) -> n__s(X) activate(n__0()) -> 0() activate(n__plus(X1,X2)) -> plus(X1,X2) activate(n__isNat(X)) -> isNat(X) activate(n__s(X)) -> s(X) activate(X) -> X Proof: DP Processor: DPs: U11#(tt(),N) -> activate#(N) U21#(tt(),M,N) -> activate#(M) U21#(tt(),M,N) -> activate#(N) U21#(tt(),M,N) -> plus#(activate(N),activate(M)) U21#(tt(),M,N) -> s#(plus(activate(N),activate(M))) and#(tt(),X) -> activate#(X) isNat#(n__plus(V1,V2)) -> activate#(V2) isNat#(n__plus(V1,V2)) -> activate#(V1) isNat#(n__plus(V1,V2)) -> isNat#(activate(V1)) isNat#(n__plus(V1,V2)) -> and#(isNat(activate(V1)),n__isNat(activate(V2))) isNat#(n__s(V1)) -> activate#(V1) isNat#(n__s(V1)) -> isNat#(activate(V1)) plus#(N,0()) -> isNat#(N) plus#(N,0()) -> U11#(isNat(N),N) plus#(N,s(M)) -> isNat#(M) plus#(N,s(M)) -> and#(isNat(M),n__isNat(N)) plus#(N,s(M)) -> U21#(and(isNat(M),n__isNat(N)),M,N) activate#(n__0()) -> 0#() activate#(n__plus(X1,X2)) -> plus#(X1,X2) activate#(n__isNat(X)) -> isNat#(X) activate#(n__s(X)) -> s#(X) TRS: U11(tt(),N) -> activate(N) U21(tt(),M,N) -> s(plus(activate(N),activate(M))) and(tt(),X) -> activate(X) isNat(n__0()) -> tt() isNat(n__plus(V1,V2)) -> and(isNat(activate(V1)),n__isNat(activate(V2))) isNat(n__s(V1)) -> isNat(activate(V1)) plus(N,0()) -> U11(isNat(N),N) plus(N,s(M)) -> U21(and(isNat(M),n__isNat(N)),M,N) 0() -> n__0() plus(X1,X2) -> n__plus(X1,X2) isNat(X) -> n__isNat(X) s(X) -> n__s(X) activate(n__0()) -> 0() activate(n__plus(X1,X2)) -> plus(X1,X2) activate(n__isNat(X)) -> isNat(X) activate(n__s(X)) -> s(X) activate(X) -> X TDG Processor: DPs: U11#(tt(),N) -> activate#(N) U21#(tt(),M,N) -> activate#(M) U21#(tt(),M,N) -> activate#(N) U21#(tt(),M,N) -> plus#(activate(N),activate(M)) U21#(tt(),M,N) -> s#(plus(activate(N),activate(M))) and#(tt(),X) -> activate#(X) isNat#(n__plus(V1,V2)) -> activate#(V2) isNat#(n__plus(V1,V2)) -> activate#(V1) isNat#(n__plus(V1,V2)) -> isNat#(activate(V1)) isNat#(n__plus(V1,V2)) -> and#(isNat(activate(V1)),n__isNat(activate(V2))) isNat#(n__s(V1)) -> activate#(V1) isNat#(n__s(V1)) -> isNat#(activate(V1)) plus#(N,0()) -> isNat#(N) plus#(N,0()) -> U11#(isNat(N),N) plus#(N,s(M)) -> isNat#(M) plus#(N,s(M)) -> and#(isNat(M),n__isNat(N)) plus#(N,s(M)) -> U21#(and(isNat(M),n__isNat(N)),M,N) activate#(n__0()) -> 0#() activate#(n__plus(X1,X2)) -> plus#(X1,X2) activate#(n__isNat(X)) -> isNat#(X) activate#(n__s(X)) -> s#(X) TRS: U11(tt(),N) -> activate(N) U21(tt(),M,N) -> s(plus(activate(N),activate(M))) and(tt(),X) -> activate(X) isNat(n__0()) -> tt() isNat(n__plus(V1,V2)) -> and(isNat(activate(V1)),n__isNat(activate(V2))) isNat(n__s(V1)) -> isNat(activate(V1)) plus(N,0()) -> U11(isNat(N),N) plus(N,s(M)) -> U21(and(isNat(M),n__isNat(N)),M,N) 0() -> n__0() plus(X1,X2) -> n__plus(X1,X2) isNat(X) -> n__isNat(X) s(X) -> n__s(X) activate(n__0()) -> 0() popout

output may be truncated. 'popout' for the full output.

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all output return to TRS Standard