details

property	value
status	complete
benchmark	PEANO_nosorts_GM.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n185.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.162465 seconds
cpu usage	0.174244
user time	0.114315
system time	0.059929
max virtual memory	113188.0
max residence set size	6712.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S M:S N:S X:S X1:S X2:S) (RULES a__and(tt,X:S) -> mark(X:S) a__and(X1:S,X2:S) -> and(X1:S,X2:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> s(a__plus(mark(N:S),mark(M:S))) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(and(X1:S,X2:S)) -> a__and(mark(X1:S),X2:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt ) Problem 1: Dependency Pairs Processor: -> Pairs: A__AND(tt,X:S) -> MARK(X:S) A__PLUS(N:S,0) -> MARK(N:S) A__PLUS(N:S,s(M:S)) -> A__PLUS(mark(N:S),mark(M:S)) A__PLUS(N:S,s(M:S)) -> MARK(M:S) A__PLUS(N:S,s(M:S)) -> MARK(N:S) MARK(and(X1:S,X2:S)) -> A__AND(mark(X1:S),X2:S) MARK(and(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> A__PLUS(mark(X1:S),mark(X2:S)) MARK(plus(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> MARK(X2:S) MARK(s(X:S)) -> MARK(X:S) -> Rules: a__and(tt,X:S) -> mark(X:S) a__and(X1:S,X2:S) -> and(X1:S,X2:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> s(a__plus(mark(N:S),mark(M:S))) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(and(X1:S,X2:S)) -> a__and(mark(X1:S),X2:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt Problem 1: SCC Processor: -> Pairs: A__AND(tt,X:S) -> MARK(X:S) A__PLUS(N:S,0) -> MARK(N:S) A__PLUS(N:S,s(M:S)) -> A__PLUS(mark(N:S),mark(M:S)) A__PLUS(N:S,s(M:S)) -> MARK(M:S) A__PLUS(N:S,s(M:S)) -> MARK(N:S) MARK(and(X1:S,X2:S)) -> A__AND(mark(X1:S),X2:S) MARK(and(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> A__PLUS(mark(X1:S),mark(X2:S)) MARK(plus(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> MARK(X2:S) MARK(s(X:S)) -> MARK(X:S) -> Rules: a__and(tt,X:S) -> mark(X:S) a__and(X1:S,X2:S) -> and(X1:S,X2:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> s(a__plus(mark(N:S),mark(M:S))) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(and(X1:S,X2:S)) -> a__and(mark(X1:S),X2:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt ->Strongly Connected Components: ->->Cycle: ->->-> Pairs: A__AND(tt,X:S) -> MARK(X:S) A__PLUS(N:S,0) -> MARK(N:S) A__PLUS(N:S,s(M:S)) -> A__PLUS(mark(N:S),mark(M:S)) A__PLUS(N:S,s(M:S)) -> MARK(M:S) A__PLUS(N:S,s(M:S)) -> MARK(N:S) MARK(and(X1:S,X2:S)) -> A__AND(mark(X1:S),X2:S) MARK(and(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> A__PLUS(mark(X1:S),mark(X2:S)) MARK(plus(X1:S,X2:S)) -> MARK(X1:S) MARK(plus(X1:S,X2:S)) -> MARK(X2:S) MARK(s(X:S)) -> MARK(X:S) ->->-> Rules: a__and(tt,X:S) -> mark(X:S) a__and(X1:S,X2:S) -> and(X1:S,X2:S) a__plus(N:S,0) -> mark(N:S) a__plus(N:S,s(M:S)) -> s(a__plus(mark(N:S),mark(M:S))) a__plus(X1:S,X2:S) -> plus(X1:S,X2:S) mark(0) -> 0 mark(and(X1:S,X2:S)) -> a__and(mark(X1:S),X2:S) mark(plus(X1:S,X2:S)) -> a__plus(mark(X1:S),mark(X2:S)) mark(s(X:S)) -> s(mark(X:S)) mark(tt) -> tt Problem 1: Reduction Pair Processor: popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Standard