details

property	value
status	complete
benchmark	OvConsOS_nokinds_noand_GM.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n074.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.920653 seconds
cpu usage	0.904233
user time	0.789871
system time	0.114362
max virtual memory	452896.0
max residence set size	12520.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S IL:S L:S M:S N:S V:S V1:S V2:S X:S X1:S X2:S X3:S X4:S) (RULES a__U11(tt) -> tt a__U11(X:S) -> U11(X:S) a__U21(tt) -> tt a__U21(X:S) -> U21(X:S) a__U31(tt) -> tt a__U31(X:S) -> U31(X:S) a__U41(tt,V2:S) -> a__U42(a__isNatIList(V2:S)) a__U41(X1:S,X2:S) -> U41(X1:S,X2:S) a__U42(tt) -> tt a__U42(X:S) -> U42(X:S) a__U51(tt,V2:S) -> a__U52(a__isNatList(V2:S)) a__U51(X1:S,X2:S) -> U51(X1:S,X2:S) a__U52(tt) -> tt a__U52(X:S) -> U52(X:S) a__U61(tt,V2:S) -> a__U62(a__isNatIList(V2:S)) a__U61(X1:S,X2:S) -> U61(X1:S,X2:S) a__U62(tt) -> tt a__U62(X:S) -> U62(X:S) a__U71(tt,L:S,N:S) -> a__U72(a__isNat(N:S),L:S) a__U71(X1:S,X2:S,X3:S) -> U71(X1:S,X2:S,X3:S) a__U72(tt,L:S) -> s(a__length(mark(L:S))) a__U72(X1:S,X2:S) -> U72(X1:S,X2:S) a__U81(tt) -> nil a__U81(X:S) -> U81(X:S) a__U91(tt,IL:S,M:S,N:S) -> a__U92(a__isNat(M:S),IL:S,M:S,N:S) a__U91(X1:S,X2:S,X3:S,X4:S) -> U91(X1:S,X2:S,X3:S,X4:S) a__U92(tt,IL:S,M:S,N:S) -> a__U93(a__isNat(N:S),IL:S,M:S,N:S) a__U92(X1:S,X2:S,X3:S,X4:S) -> U92(X1:S,X2:S,X3:S,X4:S) a__U93(tt,IL:S,M:S,N:S) -> cons(mark(N:S),take(M:S,IL:S)) a__U93(X1:S,X2:S,X3:S,X4:S) -> U93(X1:S,X2:S,X3:S,X4:S) a__isNat(0) -> tt a__isNat(length(V1:S)) -> a__U11(a__isNatList(V1:S)) a__isNat(s(V1:S)) -> a__U21(a__isNat(V1:S)) a__isNat(X:S) -> isNat(X:S) a__isNatIList(cons(V1:S,V2:S)) -> a__U41(a__isNat(V1:S),V2:S) a__isNatIList(zeros) -> tt a__isNatIList(V:S) -> a__U31(a__isNatList(V:S)) a__isNatIList(X:S) -> isNatIList(X:S) a__isNatList(cons(V1:S,V2:S)) -> a__U51(a__isNat(V1:S),V2:S) a__isNatList(nil) -> tt a__isNatList(take(V1:S,V2:S)) -> a__U61(a__isNat(V1:S),V2:S) a__isNatList(X:S) -> isNatList(X:S) a__length(cons(N:S,L:S)) -> a__U71(a__isNatList(L:S),L:S,N:S) a__length(nil) -> 0 a__length(X:S) -> length(X:S) a__take(0,IL:S) -> a__U81(a__isNatIList(IL:S)) a__take(s(M:S),cons(N:S,IL:S)) -> a__U91(a__isNatIList(IL:S),IL:S,M:S,N:S) a__take(X1:S,X2:S) -> take(X1:S,X2:S) a__zeros -> cons(0,zeros) a__zeros -> zeros mark(0) -> 0 mark(U11(X:S)) -> a__U11(mark(X:S)) mark(U21(X:S)) -> a__U21(mark(X:S)) mark(U31(X:S)) -> a__U31(mark(X:S)) mark(U41(X1:S,X2:S)) -> a__U41(mark(X1:S),X2:S) mark(U42(X:S)) -> a__U42(mark(X:S)) mark(U51(X1:S,X2:S)) -> a__U51(mark(X1:S),X2:S) mark(U52(X:S)) -> a__U52(mark(X:S)) mark(U61(X1:S,X2:S)) -> a__U61(mark(X1:S),X2:S) mark(U62(X:S)) -> a__U62(mark(X:S)) mark(U71(X1:S,X2:S,X3:S)) -> a__U71(mark(X1:S),X2:S,X3:S) mark(U72(X1:S,X2:S)) -> a__U72(mark(X1:S),X2:S) mark(U81(X:S)) -> a__U81(mark(X:S)) mark(U91(X1:S,X2:S,X3:S,X4:S)) -> a__U91(mark(X1:S),X2:S,X3:S,X4:S) mark(U92(X1:S,X2:S,X3:S,X4:S)) -> a__U92(mark(X1:S),X2:S,X3:S,X4:S) mark(U93(X1:S,X2:S,X3:S,X4:S)) -> a__U93(mark(X1:S),X2:S,X3:S,X4:S) mark(cons(X1:S,X2:S)) -> cons(mark(X1:S),X2:S) mark(isNat(X:S)) -> a__isNat(X:S) mark(isNatIList(X:S)) -> a__isNatIList(X:S) mark(isNatList(X:S)) -> a__isNatList(X:S) mark(length(X:S)) -> a__length(mark(X:S)) mark(nil) -> nil mark(s(X:S)) -> s(mark(X:S)) mark(take(X1:S,X2:S)) -> a__take(mark(X1:S),mark(X2:S)) mark(tt) -> tt mark(zeros) -> a__zeros ) Problem 1: Dependency Pairs Processor: -> Pairs: A__U41(tt,V2:S) -> A__U42(a__isNatIList(V2:S)) A__U41(tt,V2:S) -> A__ISNATILIST(V2:S) A__U51(tt,V2:S) -> A__U52(a__isNatList(V2:S)) A__U51(tt,V2:S) -> A__ISNATLIST(V2:S) A__U61(tt,V2:S) -> A__U62(a__isNatIList(V2:S)) A__U61(tt,V2:S) -> A__ISNATILIST(V2:S) A__U71(tt,L:S,N:S) -> A__U72(a__isNat(N:S),L:S) A__U71(tt,L:S,N:S) -> A__ISNAT(N:S) A__U72(tt,L:S) -> A__LENGTH(mark(L:S)) A__U72(tt,L:S) -> MARK(L:S) A__U91(tt,IL:S,M:S,N:S) -> A__U92(a__isNat(M:S),IL:S,M:S,N:S) A__U91(tt,IL:S,M:S,N:S) -> A__ISNAT(M:S) popout

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actions

all output return to TRS Standard