details

property	value
status	complete
benchmark	PEANO_complete_noand_GM.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n174.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	ttt2-1.20
configuration	ttt2
runtime (wallclock)	19.9456 seconds
cpu usage	74.3725
user time	70.3922
system time	3.98023
max virtual memory	6768592.0
max residence set size	208608.0

stage attributes

key	value
starexec-result	YES

output

YES Problem: a__U11(tt(),V1,V2) -> a__U12(a__isNatKind(V1),V1,V2) a__U12(tt(),V1,V2) -> a__U13(a__isNatKind(V2),V1,V2) a__U13(tt(),V1,V2) -> a__U14(a__isNatKind(V2),V1,V2) a__U14(tt(),V1,V2) -> a__U15(a__isNat(V1),V2) a__U15(tt(),V2) -> a__U16(a__isNat(V2)) a__U16(tt()) -> tt() a__U21(tt(),V1) -> a__U22(a__isNatKind(V1),V1) a__U22(tt(),V1) -> a__U23(a__isNat(V1)) a__U23(tt()) -> tt() a__U31(tt(),V2) -> a__U32(a__isNatKind(V2)) a__U32(tt()) -> tt() a__U41(tt()) -> tt() a__U51(tt(),N) -> a__U52(a__isNatKind(N),N) a__U52(tt(),N) -> mark(N) a__U61(tt(),M,N) -> a__U62(a__isNatKind(M),M,N) a__U62(tt(),M,N) -> a__U63(a__isNat(N),M,N) a__U63(tt(),M,N) -> a__U64(a__isNatKind(N),M,N) a__U64(tt(),M,N) -> s(a__plus(mark(N),mark(M))) a__isNat(0()) -> tt() a__isNat(plus(V1,V2)) -> a__U11(a__isNatKind(V1),V1,V2) a__isNat(s(V1)) -> a__U21(a__isNatKind(V1),V1) a__isNatKind(0()) -> tt() a__isNatKind(plus(V1,V2)) -> a__U31(a__isNatKind(V1),V2) a__isNatKind(s(V1)) -> a__U41(a__isNatKind(V1)) a__plus(N,0()) -> a__U51(a__isNat(N),N) a__plus(N,s(M)) -> a__U61(a__isNat(M),M,N) mark(U11(X1,X2,X3)) -> a__U11(mark(X1),X2,X3) mark(U12(X1,X2,X3)) -> a__U12(mark(X1),X2,X3) mark(isNatKind(X)) -> a__isNatKind(X) mark(U13(X1,X2,X3)) -> a__U13(mark(X1),X2,X3) mark(U14(X1,X2,X3)) -> a__U14(mark(X1),X2,X3) mark(U15(X1,X2)) -> a__U15(mark(X1),X2) mark(isNat(X)) -> a__isNat(X) mark(U16(X)) -> a__U16(mark(X)) mark(U21(X1,X2)) -> a__U21(mark(X1),X2) mark(U22(X1,X2)) -> a__U22(mark(X1),X2) mark(U23(X)) -> a__U23(mark(X)) mark(U31(X1,X2)) -> a__U31(mark(X1),X2) mark(U32(X)) -> a__U32(mark(X)) mark(U41(X)) -> a__U41(mark(X)) mark(U51(X1,X2)) -> a__U51(mark(X1),X2) mark(U52(X1,X2)) -> a__U52(mark(X1),X2) mark(U61(X1,X2,X3)) -> a__U61(mark(X1),X2,X3) mark(U62(X1,X2,X3)) -> a__U62(mark(X1),X2,X3) mark(U63(X1,X2,X3)) -> a__U63(mark(X1),X2,X3) mark(U64(X1,X2,X3)) -> a__U64(mark(X1),X2,X3) mark(plus(X1,X2)) -> a__plus(mark(X1),mark(X2)) mark(tt()) -> tt() mark(s(X)) -> s(mark(X)) mark(0()) -> 0() a__U11(X1,X2,X3) -> U11(X1,X2,X3) a__U12(X1,X2,X3) -> U12(X1,X2,X3) a__isNatKind(X) -> isNatKind(X) a__U13(X1,X2,X3) -> U13(X1,X2,X3) a__U14(X1,X2,X3) -> U14(X1,X2,X3) a__U15(X1,X2) -> U15(X1,X2) a__isNat(X) -> isNat(X) a__U16(X) -> U16(X) a__U21(X1,X2) -> U21(X1,X2) a__U22(X1,X2) -> U22(X1,X2) a__U23(X) -> U23(X) a__U31(X1,X2) -> U31(X1,X2) a__U32(X) -> U32(X) a__U41(X) -> U41(X) a__U51(X1,X2) -> U51(X1,X2) a__U52(X1,X2) -> U52(X1,X2) a__U61(X1,X2,X3) -> U61(X1,X2,X3) a__U62(X1,X2,X3) -> U62(X1,X2,X3) a__U63(X1,X2,X3) -> U63(X1,X2,X3) a__U64(X1,X2,X3) -> U64(X1,X2,X3) a__plus(X1,X2) -> plus(X1,X2) Proof: DP Processor: DPs: a__U11#(tt(),V1,V2) -> a__isNatKind#(V1) a__U11#(tt(),V1,V2) -> a__U12#(a__isNatKind(V1),V1,V2) a__U12#(tt(),V1,V2) -> a__isNatKind#(V2) a__U12#(tt(),V1,V2) -> a__U13#(a__isNatKind(V2),V1,V2) a__U13#(tt(),V1,V2) -> a__isNatKind#(V2) a__U13#(tt(),V1,V2) -> a__U14#(a__isNatKind(V2),V1,V2) a__U14#(tt(),V1,V2) -> a__isNat#(V1) a__U14#(tt(),V1,V2) -> a__U15#(a__isNat(V1),V2) a__U15#(tt(),V2) -> a__isNat#(V2) a__U15#(tt(),V2) -> a__U16#(a__isNat(V2)) a__U21#(tt(),V1) -> a__isNatKind#(V1) a__U21#(tt(),V1) -> a__U22#(a__isNatKind(V1),V1) a__U22#(tt(),V1) -> a__isNat#(V1) a__U22#(tt(),V1) -> a__U23#(a__isNat(V1)) a__U31#(tt(),V2) -> a__isNatKind#(V2) a__U31#(tt(),V2) -> a__U32#(a__isNatKind(V2)) a__U51#(tt(),N) -> a__isNatKind#(N) a__U51#(tt(),N) -> a__U52#(a__isNatKind(N),N) a__U52#(tt(),N) -> mark#(N) a__U61#(tt(),M,N) -> a__isNatKind#(M) a__U61#(tt(),M,N) -> a__U62#(a__isNatKind(M),M,N) a__U62#(tt(),M,N) -> a__isNat#(N) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to TRS Standard