details

property	value
status	complete
benchmark	PEANO_complete_FR.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n192.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	2.17287 seconds
cpu usage	2.25026
user time	1.95454
system time	0.295724
max virtual memory	711232.0
max residence set size	15708.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S M:S N:S V1:S V2:S X:S X1:S X2:S) (RULES 0 -> n__0 U11(tt,V1:S,V2:S) -> U12(isNat(activate(V1:S)),activate(V2:S)) U12(tt,V2:S) -> U13(isNat(activate(V2:S))) U13(tt) -> tt U21(tt,V1:S) -> U22(isNat(activate(V1:S))) U22(tt) -> tt U31(tt,N:S) -> activate(N:S) U41(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) activate(n__0) -> 0 activate(n__and(X1:S,X2:S)) -> and(activate(X1:S),X2:S) activate(n__isNat(X:S)) -> isNat(X:S) activate(n__isNatKind(X:S)) -> isNatKind(X:S) activate(n__plus(X1:S,X2:S)) -> plus(activate(X1:S),activate(X2:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(X:S) -> X:S and(tt,X:S) -> activate(X:S) and(X1:S,X2:S) -> n__and(X1:S,X2:S) isNat(n__0) -> tt isNat(n__plus(V1:S,V2:S)) -> U11(and(isNatKind(activate(V1:S)),n__isNatKind(activate(V2:S))),activate(V1:S),activate(V2:S)) isNat(n__s(V1:S)) -> U21(isNatKind(activate(V1:S)),activate(V1:S)) isNat(X:S) -> n__isNat(X:S) isNatKind(n__0) -> tt isNatKind(n__plus(V1:S,V2:S)) -> and(isNatKind(activate(V1:S)),n__isNatKind(activate(V2:S))) isNatKind(n__s(V1:S)) -> isNatKind(activate(V1:S)) isNatKind(X:S) -> n__isNatKind(X:S) plus(N:S,0) -> U31(and(isNat(N:S),n__isNatKind(N:S)),N:S) plus(N:S,s(M:S)) -> U41(and(and(isNat(M:S),n__isNatKind(M:S)),n__and(n__isNat(N:S),n__isNatKind(N:S))),M:S,N:S) plus(X1:S,X2:S) -> n__plus(X1:S,X2:S) s(X:S) -> n__s(X:S) ) Problem 1: Dependency Pairs Processor: -> Pairs: U11#(tt,V1:S,V2:S) -> U12#(isNat(activate(V1:S)),activate(V2:S)) U11#(tt,V1:S,V2:S) -> ACTIVATE(V1:S) U11#(tt,V1:S,V2:S) -> ACTIVATE(V2:S) U11#(tt,V1:S,V2:S) -> ISNAT(activate(V1:S)) U12#(tt,V2:S) -> U13#(isNat(activate(V2:S))) U12#(tt,V2:S) -> ACTIVATE(V2:S) U12#(tt,V2:S) -> ISNAT(activate(V2:S)) U21#(tt,V1:S) -> U22#(isNat(activate(V1:S))) U21#(tt,V1:S) -> ACTIVATE(V1:S) U21#(tt,V1:S) -> ISNAT(activate(V1:S)) U31#(tt,N:S) -> ACTIVATE(N:S) U41#(tt,M:S,N:S) -> ACTIVATE(M:S) U41#(tt,M:S,N:S) -> ACTIVATE(N:S) U41#(tt,M:S,N:S) -> PLUS(activate(N:S),activate(M:S)) U41#(tt,M:S,N:S) -> S(plus(activate(N:S),activate(M:S))) ACTIVATE(n__0) -> 0# ACTIVATE(n__and(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__and(X1:S,X2:S)) -> AND(activate(X1:S),X2:S) ACTIVATE(n__isNat(X:S)) -> ISNAT(X:S) ACTIVATE(n__isNatKind(X:S)) -> ISNATKIND(X:S) ACTIVATE(n__plus(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__plus(X1:S,X2:S)) -> ACTIVATE(X2:S) ACTIVATE(n__plus(X1:S,X2:S)) -> PLUS(activate(X1:S),activate(X2:S)) ACTIVATE(n__s(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__s(X:S)) -> S(activate(X:S)) AND(tt,X:S) -> ACTIVATE(X:S) ISNAT(n__plus(V1:S,V2:S)) -> U11#(and(isNatKind(activate(V1:S)),n__isNatKind(activate(V2:S))),activate(V1:S),activate(V2:S)) ISNAT(n__plus(V1:S,V2:S)) -> ACTIVATE(V1:S) ISNAT(n__plus(V1:S,V2:S)) -> ACTIVATE(V2:S) ISNAT(n__plus(V1:S,V2:S)) -> AND(isNatKind(activate(V1:S)),n__isNatKind(activate(V2:S))) ISNAT(n__plus(V1:S,V2:S)) -> ISNATKIND(activate(V1:S)) ISNAT(n__s(V1:S)) -> U21#(isNatKind(activate(V1:S)),activate(V1:S)) ISNAT(n__s(V1:S)) -> ACTIVATE(V1:S) ISNAT(n__s(V1:S)) -> ISNATKIND(activate(V1:S)) ISNATKIND(n__plus(V1:S,V2:S)) -> ACTIVATE(V1:S) ISNATKIND(n__plus(V1:S,V2:S)) -> ACTIVATE(V2:S) ISNATKIND(n__plus(V1:S,V2:S)) -> AND(isNatKind(activate(V1:S)),n__isNatKind(activate(V2:S))) ISNATKIND(n__plus(V1:S,V2:S)) -> ISNATKIND(activate(V1:S)) ISNATKIND(n__s(V1:S)) -> ACTIVATE(V1:S) ISNATKIND(n__s(V1:S)) -> ISNATKIND(activate(V1:S)) PLUS(N:S,0) -> U31#(and(isNat(N:S),n__isNatKind(N:S)),N:S) PLUS(N:S,0) -> AND(isNat(N:S),n__isNatKind(N:S)) PLUS(N:S,0) -> ISNAT(N:S) PLUS(N:S,s(M:S)) -> U41#(and(and(isNat(M:S),n__isNatKind(M:S)),n__and(n__isNat(N:S),n__isNatKind(N:S))),M:S,N:S) PLUS(N:S,s(M:S)) -> AND(and(isNat(M:S),n__isNatKind(M:S)),n__and(n__isNat(N:S),n__isNatKind(N:S))) PLUS(N:S,s(M:S)) -> AND(isNat(M:S),n__isNatKind(M:S)) PLUS(N:S,s(M:S)) -> ISNAT(M:S) -> Rules: 0 -> n__0 U11(tt,V1:S,V2:S) -> U12(isNat(activate(V1:S)),activate(V2:S)) U12(tt,V2:S) -> U13(isNat(activate(V2:S))) U13(tt) -> tt U21(tt,V1:S) -> U22(isNat(activate(V1:S))) U22(tt) -> tt U31(tt,N:S) -> activate(N:S) U41(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) activate(n__0) -> 0 activate(n__and(X1:S,X2:S)) -> and(activate(X1:S),X2:S) activate(n__isNat(X:S)) -> isNat(X:S) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to TRS Standard