details

property	value
status	complete
benchmark	PEANO_nokinds-noand_FR.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n183.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.713745 seconds
cpu usage	0.688672
user time	0.521491
system time	0.167181
max virtual memory	707376.0
max residence set size	10340.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S M:S N:S V1:S V2:S X:S X1:S X2:S) (RULES 0 -> n__0 U11(tt,V2:S) -> U12(isNat(activate(V2:S))) U12(tt) -> tt U21(tt) -> tt U31(tt,N:S) -> activate(N:S) U41(tt,M:S,N:S) -> U42(isNat(activate(N:S)),activate(M:S),activate(N:S)) U42(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) activate(n__0) -> 0 activate(n__plus(X1:S,X2:S)) -> plus(activate(X1:S),activate(X2:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(X:S) -> X:S isNat(n__0) -> tt isNat(n__plus(V1:S,V2:S)) -> U11(isNat(activate(V1:S)),activate(V2:S)) isNat(n__s(V1:S)) -> U21(isNat(activate(V1:S))) plus(N:S,0) -> U31(isNat(N:S),N:S) plus(N:S,s(M:S)) -> U41(isNat(M:S),M:S,N:S) plus(X1:S,X2:S) -> n__plus(X1:S,X2:S) s(X:S) -> n__s(X:S) ) Problem 1: Dependency Pairs Processor: -> Pairs: U11#(tt,V2:S) -> U12#(isNat(activate(V2:S))) U11#(tt,V2:S) -> ACTIVATE(V2:S) U11#(tt,V2:S) -> ISNAT(activate(V2:S)) U31#(tt,N:S) -> ACTIVATE(N:S) U41#(tt,M:S,N:S) -> U42#(isNat(activate(N:S)),activate(M:S),activate(N:S)) U41#(tt,M:S,N:S) -> ACTIVATE(M:S) U41#(tt,M:S,N:S) -> ACTIVATE(N:S) U41#(tt,M:S,N:S) -> ISNAT(activate(N:S)) U42#(tt,M:S,N:S) -> ACTIVATE(M:S) U42#(tt,M:S,N:S) -> ACTIVATE(N:S) U42#(tt,M:S,N:S) -> PLUS(activate(N:S),activate(M:S)) U42#(tt,M:S,N:S) -> S(plus(activate(N:S),activate(M:S))) ACTIVATE(n__0) -> 0# ACTIVATE(n__plus(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__plus(X1:S,X2:S)) -> ACTIVATE(X2:S) ACTIVATE(n__plus(X1:S,X2:S)) -> PLUS(activate(X1:S),activate(X2:S)) ACTIVATE(n__s(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__s(X:S)) -> S(activate(X:S)) ISNAT(n__plus(V1:S,V2:S)) -> U11#(isNat(activate(V1:S)),activate(V2:S)) ISNAT(n__plus(V1:S,V2:S)) -> ACTIVATE(V1:S) ISNAT(n__plus(V1:S,V2:S)) -> ACTIVATE(V2:S) ISNAT(n__plus(V1:S,V2:S)) -> ISNAT(activate(V1:S)) ISNAT(n__s(V1:S)) -> U21#(isNat(activate(V1:S))) ISNAT(n__s(V1:S)) -> ACTIVATE(V1:S) ISNAT(n__s(V1:S)) -> ISNAT(activate(V1:S)) PLUS(N:S,0) -> U31#(isNat(N:S),N:S) PLUS(N:S,0) -> ISNAT(N:S) PLUS(N:S,s(M:S)) -> U41#(isNat(M:S),M:S,N:S) PLUS(N:S,s(M:S)) -> ISNAT(M:S) -> Rules: 0 -> n__0 U11(tt,V2:S) -> U12(isNat(activate(V2:S))) U12(tt) -> tt U21(tt) -> tt U31(tt,N:S) -> activate(N:S) U41(tt,M:S,N:S) -> U42(isNat(activate(N:S)),activate(M:S),activate(N:S)) U42(tt,M:S,N:S) -> s(plus(activate(N:S),activate(M:S))) activate(n__0) -> 0 activate(n__plus(X1:S,X2:S)) -> plus(activate(X1:S),activate(X2:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(X:S) -> X:S isNat(n__0) -> tt isNat(n__plus(V1:S,V2:S)) -> U11(isNat(activate(V1:S)),activate(V2:S)) isNat(n__s(V1:S)) -> U21(isNat(activate(V1:S))) plus(N:S,0) -> U31(isNat(N:S),N:S) plus(N:S,s(M:S)) -> U41(isNat(M:S),M:S,N:S) plus(X1:S,X2:S) -> n__plus(X1:S,X2:S) s(X:S) -> n__s(X:S) Problem 1: SCC Processor: -> Pairs: U11#(tt,V2:S) -> U12#(isNat(activate(V2:S))) U11#(tt,V2:S) -> ACTIVATE(V2:S) U11#(tt,V2:S) -> ISNAT(activate(V2:S)) U31#(tt,N:S) -> ACTIVATE(N:S) U41#(tt,M:S,N:S) -> U42#(isNat(activate(N:S)),activate(M:S),activate(N:S)) U41#(tt,M:S,N:S) -> ACTIVATE(M:S) U41#(tt,M:S,N:S) -> ACTIVATE(N:S) U41#(tt,M:S,N:S) -> ISNAT(activate(N:S)) U42#(tt,M:S,N:S) -> ACTIVATE(M:S) U42#(tt,M:S,N:S) -> ACTIVATE(N:S) U42#(tt,M:S,N:S) -> PLUS(activate(N:S),activate(M:S)) U42#(tt,M:S,N:S) -> S(plus(activate(N:S),activate(M:S))) ACTIVATE(n__0) -> 0# ACTIVATE(n__plus(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__plus(X1:S,X2:S)) -> ACTIVATE(X2:S) ACTIVATE(n__plus(X1:S,X2:S)) -> PLUS(activate(X1:S),activate(X2:S)) ACTIVATE(n__s(X:S)) -> ACTIVATE(X:S) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Standard