details

property	value
status	complete
benchmark	Ex7_BLR02_FR.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n074.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.171132 seconds
cpu usage	0.183264
user time	0.112191
system time	0.071073
max virtual memory	113188.0
max residence set size	7164.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S N:S X:S X1:S X2:S XS:S) (RULES 2nd(cons(X:S,XS:S)) -> head(activate(XS:S)) activate(n__from(X:S)) -> from(activate(X:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(n__take(X1:S,X2:S)) -> take(activate(X1:S),activate(X2:S)) activate(X:S) -> X:S from(X:S) -> cons(X:S,n__from(n__s(X:S))) from(X:S) -> n__from(X:S) head(cons(X:S,XS:S)) -> X:S s(X:S) -> n__s(X:S) sel(s(N:S),cons(X:S,XS:S)) -> sel(N:S,activate(XS:S)) sel(0,cons(X:S,XS:S)) -> X:S take(s(N:S),cons(X:S,XS:S)) -> cons(X:S,n__take(N:S,activate(XS:S))) take(0,XS:S) -> nil take(X1:S,X2:S) -> n__take(X1:S,X2:S) ) Problem 1: Dependency Pairs Processor: -> Pairs: 2ND(cons(X:S,XS:S)) -> ACTIVATE(XS:S) 2ND(cons(X:S,XS:S)) -> HEAD(activate(XS:S)) ACTIVATE(n__from(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__from(X:S)) -> FROM(activate(X:S)) ACTIVATE(n__s(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__s(X:S)) -> S(activate(X:S)) ACTIVATE(n__take(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__take(X1:S,X2:S)) -> ACTIVATE(X2:S) ACTIVATE(n__take(X1:S,X2:S)) -> TAKE(activate(X1:S),activate(X2:S)) SEL(s(N:S),cons(X:S,XS:S)) -> ACTIVATE(XS:S) SEL(s(N:S),cons(X:S,XS:S)) -> SEL(N:S,activate(XS:S)) TAKE(s(N:S),cons(X:S,XS:S)) -> ACTIVATE(XS:S) -> Rules: 2nd(cons(X:S,XS:S)) -> head(activate(XS:S)) activate(n__from(X:S)) -> from(activate(X:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(n__take(X1:S,X2:S)) -> take(activate(X1:S),activate(X2:S)) activate(X:S) -> X:S from(X:S) -> cons(X:S,n__from(n__s(X:S))) from(X:S) -> n__from(X:S) head(cons(X:S,XS:S)) -> X:S s(X:S) -> n__s(X:S) sel(s(N:S),cons(X:S,XS:S)) -> sel(N:S,activate(XS:S)) sel(0,cons(X:S,XS:S)) -> X:S take(s(N:S),cons(X:S,XS:S)) -> cons(X:S,n__take(N:S,activate(XS:S))) take(0,XS:S) -> nil take(X1:S,X2:S) -> n__take(X1:S,X2:S) Problem 1: SCC Processor: -> Pairs: 2ND(cons(X:S,XS:S)) -> ACTIVATE(XS:S) 2ND(cons(X:S,XS:S)) -> HEAD(activate(XS:S)) ACTIVATE(n__from(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__from(X:S)) -> FROM(activate(X:S)) ACTIVATE(n__s(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__s(X:S)) -> S(activate(X:S)) ACTIVATE(n__take(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__take(X1:S,X2:S)) -> ACTIVATE(X2:S) ACTIVATE(n__take(X1:S,X2:S)) -> TAKE(activate(X1:S),activate(X2:S)) SEL(s(N:S),cons(X:S,XS:S)) -> ACTIVATE(XS:S) SEL(s(N:S),cons(X:S,XS:S)) -> SEL(N:S,activate(XS:S)) TAKE(s(N:S),cons(X:S,XS:S)) -> ACTIVATE(XS:S) -> Rules: 2nd(cons(X:S,XS:S)) -> head(activate(XS:S)) activate(n__from(X:S)) -> from(activate(X:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(n__take(X1:S,X2:S)) -> take(activate(X1:S),activate(X2:S)) activate(X:S) -> X:S from(X:S) -> cons(X:S,n__from(n__s(X:S))) from(X:S) -> n__from(X:S) head(cons(X:S,XS:S)) -> X:S s(X:S) -> n__s(X:S) sel(s(N:S),cons(X:S,XS:S)) -> sel(N:S,activate(XS:S)) sel(0,cons(X:S,XS:S)) -> X:S take(s(N:S),cons(X:S,XS:S)) -> cons(X:S,n__take(N:S,activate(XS:S))) take(0,XS:S) -> nil take(X1:S,X2:S) -> n__take(X1:S,X2:S) ->Strongly Connected Components: ->->Cycle: ->->-> Pairs: ACTIVATE(n__from(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__s(X:S)) -> ACTIVATE(X:S) ACTIVATE(n__take(X1:S,X2:S)) -> ACTIVATE(X1:S) ACTIVATE(n__take(X1:S,X2:S)) -> ACTIVATE(X2:S) ACTIVATE(n__take(X1:S,X2:S)) -> TAKE(activate(X1:S),activate(X2:S)) TAKE(s(N:S),cons(X:S,XS:S)) -> ACTIVATE(XS:S) ->->-> Rules: 2nd(cons(X:S,XS:S)) -> head(activate(XS:S)) activate(n__from(X:S)) -> from(activate(X:S)) activate(n__s(X:S)) -> s(activate(X:S)) activate(n__take(X1:S,X2:S)) -> take(activate(X1:S),activate(X2:S)) activate(X:S) -> X:S popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Standard