details

property	value
status	complete
benchmark	PEANO_nokinds_GM.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n173.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	ttt2-1.20
configuration	ttt2
runtime (wallclock)	15.0583 seconds
cpu usage	56.8646
user time	50.3894
system time	6.47523
max virtual memory	6179988.0
max residence set size	172396.0

stage attributes

key	value
starexec-result	YES

output

YES Problem: a__U11(tt(),N) -> mark(N) a__U21(tt(),M,N) -> s(a__plus(mark(N),mark(M))) a__and(tt(),X) -> mark(X) a__isNat(0()) -> tt() a__isNat(plus(V1,V2)) -> a__and(a__isNat(V1),isNat(V2)) a__isNat(s(V1)) -> a__isNat(V1) a__plus(N,0()) -> a__U11(a__isNat(N),N) a__plus(N,s(M)) -> a__U21(a__and(a__isNat(M),isNat(N)),M,N) mark(U11(X1,X2)) -> a__U11(mark(X1),X2) mark(U21(X1,X2,X3)) -> a__U21(mark(X1),X2,X3) mark(plus(X1,X2)) -> a__plus(mark(X1),mark(X2)) mark(and(X1,X2)) -> a__and(mark(X1),X2) mark(isNat(X)) -> a__isNat(X) mark(tt()) -> tt() mark(s(X)) -> s(mark(X)) mark(0()) -> 0() a__U11(X1,X2) -> U11(X1,X2) a__U21(X1,X2,X3) -> U21(X1,X2,X3) a__plus(X1,X2) -> plus(X1,X2) a__and(X1,X2) -> and(X1,X2) a__isNat(X) -> isNat(X) Proof: DP Processor: DPs: a__U11#(tt(),N) -> mark#(N) a__U21#(tt(),M,N) -> mark#(M) a__U21#(tt(),M,N) -> mark#(N) a__U21#(tt(),M,N) -> a__plus#(mark(N),mark(M)) a__and#(tt(),X) -> mark#(X) a__isNat#(plus(V1,V2)) -> a__isNat#(V1) a__isNat#(plus(V1,V2)) -> a__and#(a__isNat(V1),isNat(V2)) a__isNat#(s(V1)) -> a__isNat#(V1) a__plus#(N,0()) -> a__isNat#(N) a__plus#(N,0()) -> a__U11#(a__isNat(N),N) a__plus#(N,s(M)) -> a__isNat#(M) a__plus#(N,s(M)) -> a__and#(a__isNat(M),isNat(N)) a__plus#(N,s(M)) -> a__U21#(a__and(a__isNat(M),isNat(N)),M,N) mark#(U11(X1,X2)) -> mark#(X1) mark#(U11(X1,X2)) -> a__U11#(mark(X1),X2) mark#(U21(X1,X2,X3)) -> mark#(X1) mark#(U21(X1,X2,X3)) -> a__U21#(mark(X1),X2,X3) mark#(plus(X1,X2)) -> mark#(X2) mark#(plus(X1,X2)) -> mark#(X1) mark#(plus(X1,X2)) -> a__plus#(mark(X1),mark(X2)) mark#(and(X1,X2)) -> mark#(X1) mark#(and(X1,X2)) -> a__and#(mark(X1),X2) mark#(isNat(X)) -> a__isNat#(X) mark#(s(X)) -> mark#(X) TRS: a__U11(tt(),N) -> mark(N) a__U21(tt(),M,N) -> s(a__plus(mark(N),mark(M))) a__and(tt(),X) -> mark(X) a__isNat(0()) -> tt() a__isNat(plus(V1,V2)) -> a__and(a__isNat(V1),isNat(V2)) a__isNat(s(V1)) -> a__isNat(V1) a__plus(N,0()) -> a__U11(a__isNat(N),N) a__plus(N,s(M)) -> a__U21(a__and(a__isNat(M),isNat(N)),M,N) mark(U11(X1,X2)) -> a__U11(mark(X1),X2) mark(U21(X1,X2,X3)) -> a__U21(mark(X1),X2,X3) mark(plus(X1,X2)) -> a__plus(mark(X1),mark(X2)) mark(and(X1,X2)) -> a__and(mark(X1),X2) mark(isNat(X)) -> a__isNat(X) mark(tt()) -> tt() mark(s(X)) -> s(mark(X)) mark(0()) -> 0() a__U11(X1,X2) -> U11(X1,X2) a__U21(X1,X2,X3) -> U21(X1,X2,X3) a__plus(X1,X2) -> plus(X1,X2) a__and(X1,X2) -> and(X1,X2) a__isNat(X) -> isNat(X) TDG Processor: DPs: a__U11#(tt(),N) -> mark#(N) a__U21#(tt(),M,N) -> mark#(M) a__U21#(tt(),M,N) -> mark#(N) a__U21#(tt(),M,N) -> a__plus#(mark(N),mark(M)) a__and#(tt(),X) -> mark#(X) a__isNat#(plus(V1,V2)) -> a__isNat#(V1) a__isNat#(plus(V1,V2)) -> a__and#(a__isNat(V1),isNat(V2)) a__isNat#(s(V1)) -> a__isNat#(V1) a__plus#(N,0()) -> a__isNat#(N) a__plus#(N,0()) -> a__U11#(a__isNat(N),N) a__plus#(N,s(M)) -> a__isNat#(M) a__plus#(N,s(M)) -> a__and#(a__isNat(M),isNat(N)) a__plus#(N,s(M)) -> a__U21#(a__and(a__isNat(M),isNat(N)),M,N) mark#(U11(X1,X2)) -> mark#(X1) mark#(U11(X1,X2)) -> a__U11#(mark(X1),X2) mark#(U21(X1,X2,X3)) -> mark#(X1) mark#(U21(X1,X2,X3)) -> a__U21#(mark(X1),X2,X3) mark#(plus(X1,X2)) -> mark#(X2) mark#(plus(X1,X2)) -> mark#(X1) mark#(plus(X1,X2)) -> a__plus#(mark(X1),mark(X2)) mark#(and(X1,X2)) -> mark#(X1) mark#(and(X1,X2)) -> a__and#(mark(X1),X2) mark#(isNat(X)) -> a__isNat#(X) mark#(s(X)) -> mark#(X) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Standard