details

property	value
status	complete
benchmark	MYNAT_nosorts_iGM.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n192.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	ttt2-1.20
configuration	ttt2
runtime (wallclock)	4.17746 seconds
cpu usage	14.5203
user time	12.3841
system time	2.13619
max virtual memory	6120656.0
max residence set size	112024.0

stage attributes

key	value
starexec-result	YES

output

YES Problem: active(and(tt(),X)) -> mark(X) active(plus(N,0())) -> mark(N) active(plus(N,s(M))) -> mark(s(plus(N,M))) active(x(N,0())) -> mark(0()) active(x(N,s(M))) -> mark(plus(x(N,M),N)) mark(and(X1,X2)) -> active(and(mark(X1),X2)) mark(tt()) -> active(tt()) mark(plus(X1,X2)) -> active(plus(mark(X1),mark(X2))) mark(0()) -> active(0()) mark(s(X)) -> active(s(mark(X))) mark(x(X1,X2)) -> active(x(mark(X1),mark(X2))) and(mark(X1),X2) -> and(X1,X2) and(X1,mark(X2)) -> and(X1,X2) and(active(X1),X2) -> and(X1,X2) and(X1,active(X2)) -> and(X1,X2) plus(mark(X1),X2) -> plus(X1,X2) plus(X1,mark(X2)) -> plus(X1,X2) plus(active(X1),X2) -> plus(X1,X2) plus(X1,active(X2)) -> plus(X1,X2) s(mark(X)) -> s(X) s(active(X)) -> s(X) x(mark(X1),X2) -> x(X1,X2) x(X1,mark(X2)) -> x(X1,X2) x(active(X1),X2) -> x(X1,X2) x(X1,active(X2)) -> x(X1,X2) Proof: DP Processor: DPs: active#(and(tt(),X)) -> mark#(X) active#(plus(N,0())) -> mark#(N) active#(plus(N,s(M))) -> plus#(N,M) active#(plus(N,s(M))) -> s#(plus(N,M)) active#(plus(N,s(M))) -> mark#(s(plus(N,M))) active#(x(N,0())) -> mark#(0()) active#(x(N,s(M))) -> x#(N,M) active#(x(N,s(M))) -> plus#(x(N,M),N) active#(x(N,s(M))) -> mark#(plus(x(N,M),N)) mark#(and(X1,X2)) -> mark#(X1) mark#(and(X1,X2)) -> and#(mark(X1),X2) mark#(and(X1,X2)) -> active#(and(mark(X1),X2)) mark#(tt()) -> active#(tt()) mark#(plus(X1,X2)) -> mark#(X2) mark#(plus(X1,X2)) -> mark#(X1) mark#(plus(X1,X2)) -> plus#(mark(X1),mark(X2)) mark#(plus(X1,X2)) -> active#(plus(mark(X1),mark(X2))) mark#(0()) -> active#(0()) mark#(s(X)) -> mark#(X) mark#(s(X)) -> s#(mark(X)) mark#(s(X)) -> active#(s(mark(X))) mark#(x(X1,X2)) -> mark#(X2) mark#(x(X1,X2)) -> mark#(X1) mark#(x(X1,X2)) -> x#(mark(X1),mark(X2)) mark#(x(X1,X2)) -> active#(x(mark(X1),mark(X2))) and#(mark(X1),X2) -> and#(X1,X2) and#(X1,mark(X2)) -> and#(X1,X2) and#(active(X1),X2) -> and#(X1,X2) and#(X1,active(X2)) -> and#(X1,X2) plus#(mark(X1),X2) -> plus#(X1,X2) plus#(X1,mark(X2)) -> plus#(X1,X2) plus#(active(X1),X2) -> plus#(X1,X2) plus#(X1,active(X2)) -> plus#(X1,X2) s#(mark(X)) -> s#(X) s#(active(X)) -> s#(X) x#(mark(X1),X2) -> x#(X1,X2) x#(X1,mark(X2)) -> x#(X1,X2) x#(active(X1),X2) -> x#(X1,X2) x#(X1,active(X2)) -> x#(X1,X2) TRS: active(and(tt(),X)) -> mark(X) active(plus(N,0())) -> mark(N) active(plus(N,s(M))) -> mark(s(plus(N,M))) active(x(N,0())) -> mark(0()) active(x(N,s(M))) -> mark(plus(x(N,M),N)) mark(and(X1,X2)) -> active(and(mark(X1),X2)) mark(tt()) -> active(tt()) mark(plus(X1,X2)) -> active(plus(mark(X1),mark(X2))) mark(0()) -> active(0()) mark(s(X)) -> active(s(mark(X))) mark(x(X1,X2)) -> active(x(mark(X1),mark(X2))) and(mark(X1),X2) -> and(X1,X2) and(X1,mark(X2)) -> and(X1,X2) and(active(X1),X2) -> and(X1,X2) and(X1,active(X2)) -> and(X1,X2) plus(mark(X1),X2) -> plus(X1,X2) plus(X1,mark(X2)) -> plus(X1,X2) plus(active(X1),X2) -> plus(X1,X2) plus(X1,active(X2)) -> plus(X1,X2) s(mark(X)) -> s(X) s(active(X)) -> s(X) x(mark(X1),X2) -> x(X1,X2) x(X1,mark(X2)) -> x(X1,X2) x(active(X1),X2) -> x(X1,X2) x(X1,active(X2)) -> x(X1,X2) TDG Processor: DPs: active#(and(tt(),X)) -> mark#(X) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to TRS Standard