details

property	value
status	complete
benchmark	thiemann12.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n173.star.cs.uiowa.edu
space	AProVE_07

run statistics

property	value
solver	muterm 6.0.3
configuration	default
runtime (wallclock)	0.125781 seconds
cpu usage	0.112793
user time	0.06769
system time	0.045103
max virtual memory	113188.0
max residence set size	5784.0

stage attributes

key	value
starexec-result	YES

output

YES Problem 1: (VAR v_NonEmpty:S x:S y:S) (RULES half(0) -> 0 half(s(0)) -> 0 half(s(s(x:S))) -> s(half(x:S)) if(ffalse,x:S,y:S) -> log2(half(x:S),y:S) if(ttrue,x:S,s(y:S)) -> y:S inc(0) -> 0 inc(s(x:S)) -> s(inc(x:S)) le(0,y:S) -> ttrue le(s(x:S),0) -> ffalse le(s(x:S),s(y:S)) -> le(x:S,y:S) log(x:S) -> log2(x:S,0) log2(x:S,y:S) -> if(le(x:S,s(0)),x:S,inc(y:S)) ) Problem 1: Innermost Equivalent Processor: -> Rules: half(0) -> 0 half(s(0)) -> 0 half(s(s(x:S))) -> s(half(x:S)) if(ffalse,x:S,y:S) -> log2(half(x:S),y:S) if(ttrue,x:S,s(y:S)) -> y:S inc(0) -> 0 inc(s(x:S)) -> s(inc(x:S)) le(0,y:S) -> ttrue le(s(x:S),0) -> ffalse le(s(x:S),s(y:S)) -> le(x:S,y:S) log(x:S) -> log2(x:S,0) log2(x:S,y:S) -> if(le(x:S,s(0)),x:S,inc(y:S)) -> The term rewriting system is non-overlaping or locally confluent overlay system. Therefore, innermost termination implies termination. Problem 1: Dependency Pairs Processor: -> Pairs: HALF(s(s(x:S))) -> HALF(x:S) IF(ffalse,x:S,y:S) -> HALF(x:S) IF(ffalse,x:S,y:S) -> LOG2(half(x:S),y:S) INC(s(x:S)) -> INC(x:S) LE(s(x:S),s(y:S)) -> LE(x:S,y:S) LOG(x:S) -> LOG2(x:S,0) LOG2(x:S,y:S) -> IF(le(x:S,s(0)),x:S,inc(y:S)) LOG2(x:S,y:S) -> INC(y:S) LOG2(x:S,y:S) -> LE(x:S,s(0)) -> Rules: half(0) -> 0 half(s(0)) -> 0 half(s(s(x:S))) -> s(half(x:S)) if(ffalse,x:S,y:S) -> log2(half(x:S),y:S) if(ttrue,x:S,s(y:S)) -> y:S inc(0) -> 0 inc(s(x:S)) -> s(inc(x:S)) le(0,y:S) -> ttrue le(s(x:S),0) -> ffalse le(s(x:S),s(y:S)) -> le(x:S,y:S) log(x:S) -> log2(x:S,0) log2(x:S,y:S) -> if(le(x:S,s(0)),x:S,inc(y:S)) Problem 1: SCC Processor: -> Pairs: HALF(s(s(x:S))) -> HALF(x:S) IF(ffalse,x:S,y:S) -> HALF(x:S) IF(ffalse,x:S,y:S) -> LOG2(half(x:S),y:S) INC(s(x:S)) -> INC(x:S) LE(s(x:S),s(y:S)) -> LE(x:S,y:S) LOG(x:S) -> LOG2(x:S,0) LOG2(x:S,y:S) -> IF(le(x:S,s(0)),x:S,inc(y:S)) LOG2(x:S,y:S) -> INC(y:S) LOG2(x:S,y:S) -> LE(x:S,s(0)) -> Rules: half(0) -> 0 half(s(0)) -> 0 half(s(s(x:S))) -> s(half(x:S)) if(ffalse,x:S,y:S) -> log2(half(x:S),y:S) if(ttrue,x:S,s(y:S)) -> y:S inc(0) -> 0 inc(s(x:S)) -> s(inc(x:S)) le(0,y:S) -> ttrue le(s(x:S),0) -> ffalse le(s(x:S),s(y:S)) -> le(x:S,y:S) log(x:S) -> log2(x:S,0) log2(x:S,y:S) -> if(le(x:S,s(0)),x:S,inc(y:S)) ->Strongly Connected Components: ->->Cycle: ->->-> Pairs: LE(s(x:S),s(y:S)) -> LE(x:S,y:S) ->->-> Rules: half(0) -> 0 half(s(0)) -> 0 half(s(s(x:S))) -> s(half(x:S)) popout

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