details

property	value
status	complete
benchmark	11.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n142.star.cs.uiowa.edu
space	Zantema_06

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.81591 seconds
cpu usage	3.84528
user time	3.69304
system time	0.152246
max virtual memory	1.8743788E7
max residence set size	275308.0

stage attributes

key	value
starexec-result	YES

output

YES proof of /export/starexec/sandbox/benchmark/theBenchmark.xml # AProVE Commit ID: 794c25de1cacf0d048858bcd21c9a779e1221865 marcel 20200619 unpublished dirty Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) RFCMatchBoundsTRSProof [EQUIVALENT, 29 ms] (2) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: a(l(x1)) -> l(a(x1)) a(c(x1)) -> c(a(x1)) c(a(r(x1))) -> r(a(x1)) l(r(a(x1))) -> a(l(c(c(r(x1))))) Q is empty. ---------------------------------------- (1) RFCMatchBoundsTRSProof (EQUIVALENT) Termination of the TRS R could be shown with a Match Bound [MATCHBOUNDS1,MATCHBOUNDS2] of 3. This implies Q-termination of R. The following rules were used to construct the certificate: a(l(x1)) -> l(a(x1)) a(c(x1)) -> c(a(x1)) c(a(r(x1))) -> r(a(x1)) l(r(a(x1))) -> a(l(c(c(r(x1))))) The certificate found is represented by the following graph. The certificate consists of the following enumerated nodes: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 Node 1 is start node and node 2 is final node. Those nodes are connected through the following edges: * 1 to 3 labelled l_1(0), c_1(0), r_1(0)* 1 to 4 labelled a_1(0)* 1 to 8 labelled l_1(1)* 1 to 9 labelled r_1(1)* 1 to 12 labelled a_1(1)* 1 to 16 labelled l_1(2)* 2 to 2 labelled #_1(0)* 3 to 2 labelled a_1(0)* 3 to 9 labelled l_1(1), c_1(1), r_1(1)* 3 to 17 labelled a_1(2)* 3 to 21 labelled l_1(3)* 4 to 5 labelled l_1(0)* 5 to 6 labelled c_1(0)* 6 to 7 labelled c_1(0)* 7 to 2 labelled r_1(0)* 8 to 5 labelled a_1(1)* 8 to 10 labelled c_1(1)* 9 to 2 labelled a_1(1)* 9 to 9 labelled l_1(1), c_1(1), r_1(1)* 9 to 17 labelled a_1(2)* 9 to 21 labelled l_1(3)* 10 to 6 labelled a_1(1)* 10 to 11 labelled c_1(1)* 10 to 9 labelled r_1(1)* 11 to 7 labelled a_1(1)* 12 to 13 labelled l_1(1)* 13 to 14 labelled c_1(1)* 14 to 15 labelled c_1(1)* 15 to 2 labelled r_1(1)* 15 to 17 labelled r_1(1)* 16 to 13 labelled a_1(2)* 16 to 22 labelled c_1(2)* 17 to 18 labelled l_1(2)* 18 to 19 labelled c_1(2)* 19 to 20 labelled c_1(2)* 20 to 2 labelled r_1(2)* 20 to 17 labelled r_1(2)* 21 to 18 labelled a_1(3)* 21 to 23 labelled c_1(3)* 22 to 14 labelled a_1(2)* 22 to 24 labelled c_1(2)* 22 to 26 labelled r_1(2)* 22 to 3 labelled r_1(2)* 23 to 19 labelled a_1(3)* 23 to 25 labelled c_1(3)* 23 to 27 labelled r_1(3)* 24 to 15 labelled a_1(2)* 25 to 20 labelled a_1(3)* 26 to 2 labelled a_1(2)* 26 to 9 labelled l_1(1), c_1(1), r_1(1)* 26 to 17 labelled a_1(2)* 26 to 21 labelled l_1(3)* 27 to 2 labelled a_1(3)* 27 to 17 labelled a_1(3), a_1(2)* 27 to 9 labelled l_1(1), c_1(1), r_1(1)* 27 to 21 labelled l_1(3) ---------------------------------------- (2) YES popout

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all output return to SRS Standard