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SRS Standard pair #487085645
details
property
value
status
complete
benchmark
02.xml
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n142.star.cs.uiowa.edu
space
Bouchare_06
run statistics
property
value
solver
MultumNonMulta 20 June 2020 20G sparse
configuration
default
runtime (wallclock)
0.404541 seconds
cpu usage
0.682294
user time
0.553911
system time
0.128383
max virtual memory
113188.0
max residence set size
178708.0
stage attributes
key
value
starexec-result
YES
output
YES After renaming modulo { a->0, b->1 }, it remains to prove termination of the 3-rule system { 0 1 0 -> 1 0 , 1 1 1 -> 1 0 1 , 0 0 -> 1 1 1 } The system was filtered by the following matrix interpretation of type E_J with J = {1,...,2} and dimension 3: 0 is interpreted by / \ | 1 0 1 | | 0 1 0 | | 0 1 0 | \ / 1 is interpreted by / \ | 1 0 0 | | 0 1 0 | | 0 0 0 | \ / After renaming modulo { 0->0, 1->1 }, it remains to prove termination of the 2-rule system { 0 1 0 -> 1 0 , 1 1 1 -> 1 0 1 } The system was filtered by the following matrix interpretation of type E_J with J = {1,...,2} and dimension 2: 0 is interpreted by / \ | 1 1 | | 0 1 | \ / 1 is interpreted by / \ | 1 1 | | 0 1 | \ / After renaming modulo { 1->0, 0->1 }, it remains to prove termination of the 1-rule system { 0 0 0 -> 0 1 0 } The system was filtered by the following matrix interpretation of type E_J with J = {1,...,2} and dimension 2: 0 is interpreted by / \ | 1 1 | | 0 1 | \ / 1 is interpreted by / \ | 1 0 | | 0 1 | \ / After renaming modulo { }, it remains to prove termination of the 0-rule system { } The system is trivially terminating.
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